The Growing Problem With Parasitic Extraction

Why advanced nodes are making parasitic extraction more difficult and forcing changes in design flows; flaunting the laws of physics.

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By Ed Sperling

Like everything else in semiconductor engineering at advanced process geometries, parasitic extraction is getting much more difficult at each node.

There’s more circuit data to analyze, less distance between wires and much more to sort through. In addition, a 10% error in accuracy at 90nm might have been tolerable, while at 28nm it can completely change how a chip works. And that’s only the beginning. Extraction now has to be done further up in the design cycle, with rising concerns for lower power, thinner layers of metal, new structures, and stress.

“In my opinion, this is one of the real big issues in design going forward,” said Andrew Brotman, vice president of design infrastructure at GlobalFoundries. “The parasitics associated with wires at advanced nodes is getting worse. If you deal with them too late, it hurts with time to tapeout.”

At the very least, parasitic extraction has to be moved up further in the design flow. The current thinking is that it should be part of place-and-route, but some chipmakers say it really should be considered at the architectural level for advanced designs.

“Some companies that are sensitive to these issues are addressing it,” Brotman added. “Qualcomm already is doing redundant vias. The next step is to add fill, which is extra metal to make metal densities more uniform. At 65nm and above, that was taken care of by the foundries. It was easy to keep metal away from other metal. At 45nm, the interconnects are more difficult.”

There are also a lot more of them. The harsh reality of Moore’s Law is that while it pushes transistors and wires closer together at each process node, it also adds many more of them. There’s twice as much data to crunch at each successive node even if everything worked as planned. But when it comes to interconnects, the closer they are together the greater the number of parasitic interactions. And with the emphasis on low-power designs and devices, those parasitics become even trickier to deal with effectively.

Electromigration
Physics isn’t helping the situation. Put an interconnect near a transistor, run current through it, and some of the ions strip away from the wire and move. With thicker wires, this isn’t a big problem. As wires get thinner at each process node and the spaces between them shrink, it can become a big problem.

That was one of the main reasons that chipmakers moved from aluminum interconnects to copper at 130nm. Aluminum is more prone to electromigration than copper. But even copper is showing its limits at advanced nodes. (see Figure 1)

“The problem at 40nm and below is that metal layers are thinner and electromigration is becoming a tremendous problem,” said Mahesh Tirupattur, executive vice president at Analog Bits. “We get the data from the foundries about this, but we still need to check it all. A lot of times it even requires manual checking.”

Tirupattur noted that while the existing tools and rules can handle the parasitics, the electromigration has never been effectively addressed. Electromigration has been a problem at higher currents, and it has been a problem at smaller geometries. But lowering the current to save power isn’t enough to stop the process when everything is more densely packed onto a piece of silicon.

In fact, sometimes cutting the power and creating power islands makes the issue even more complex. It’s harder to figure out where the electromigration will occur in chips if all the parts aren’t always on and not all the interconnects are in constant use.

Figure 1: Electron microscope scan of failure caused by electromigration in copper interconnect. (Courtesy of Wikipedia)

Figure 1: Electron microscope scan of failure caused by electromigration in copper interconnect. (Courtesy of Wikipedia)

Into the future
At 22nm and beyond, makers of SoCs are looking at new structures such as FinFETs and possibly even 3D stacking of chips with through-silicon vias. While 3D, in particular, may ease some issues such as analog process integration, timing closure and IP re-use, it also will dramatically raise the amount of circuit data that needs to be crunched during parasitic extraction to be able to simulate a design.

How that will affect thermal envelopes within the stacked die, what effect it will have on electromigration, which will be able to move in 3D, and how the parasitics will be mapped and removed are all big questions marks. So are the costs associated with these tasks and the time it will take to get a chip to tapeout.