March 2011 - Semiconductor Engineering

The Quest For A Better IP Integration Methodology
By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Ed Sperling With the amount of IP in SoC designs now hitting an estimated 70% to 90%, companies are scrambling to figure out a way to more consistently integrate that IP and to test that it will work as expected. This is easier said than done, however, for a number of reasons: There are numerous types of IP, ranging from I/O to logic and memory. Not all IP is of equal quality. ... » read more

Fishing For Ideas In A Bigger Pond
By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Ann Steffora Mutschler From networking to optical modeling to open source software platforms, EDA engineers are drawing from a variety of disciplines to develop tools for chip design, stretching the technology beyond its original intent. To this end, Synopsys acquired Optical Research Associates (ORA) last fall to add optical design and analysis to its portfolio. The acquisition allowed ... » read more

Keeping Up With Complexity
By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Ed Sperling There are two schools of thought in designing complex SoCs. One says that increasing complexity requires a higher level of abstraction. The other says providing enough detail to get the design right is the only effective way to do it. There are staunch proponents of both approaches, but what has been missing are bridges to tie the higher level of abstraction to the more labo... » read more

3D ICs: No Simple Answers
By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Pallab Chatterjee Just how ready is the semiconductor industry for stacked die? That was the subject of a recent panel discussion involving ARM, Atrenta, Xilinx, Samsung and Mentor Graphics. The reasoning behind 3D stacking is becoming clearer at each node. I/O count and delay times are forcing different configurations, but the time frames for these changes and the gating constraints are... » read more

Moore’s Law Revisited
By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Ed Sperling The push to 20nm and beyond is creating some interesting gyrations in the EDA industry. While tools vendors continue to work on tools for the latest process nodes, they’re also taking some significant sidesteps. The first to publicly recognize a shift is under way was Cadence, which last year issued its EDA 360 manifesto. The strategy is to continue investing in existing to... » read more

The Current State Of 3D Stacking
By Javier DeLaCruz - 31 Mar, 2011 - Comments: 0

By Javier DeLaCruz Thru-silicon-vias (TSVs) have become a very hot topic in in recent months. Ever since Xilinx reported that it is using a 2.5D TSV approach for its Virtex-7 FPGAs the industry started to salivate with the prospects of this new technology. While this technology may be accessible for larger stacked memory, FPGAs, MEMS devices, and CMOS image sensors, this does not inherently me... » read more

Interchip Connectivity
By Kurt Shuler - 31 Mar, 2011 - Comments: 0

By Kurt Shuler There has been a lot of confusion about the different standards for interchip connectivity, with many hardware developers of consumer electronics and mobile computing systems-on-chip wondering what to use. As an interconnect IP provider, I struggle with this every day when working with our customers. I wrote this article to share what I have learned. Why interchip connectivit... » read more

Speeding Tickets
By Frank Ferro - 31 Mar, 2011 - Comments: 0

By Frank Ferro Speed sells. Bells and whistles are always intriguing and fun to have, but the driver for new products is usually speed. We want to move our phones to the 4G network for faster download speeds, or replace our 802.11g home router with the new 802.11n, we want a PC with a dual-core processor to replace the single-core processor, and the list goes on. Clearly speed is an easy way t... » read more

Applying Rules Differently
By Jon McDonald - 31 Mar, 2011 - Comments: 0

By Jon McDonald Over the past few months I’ve worked with a number of customers on new designs. Thinking about how these designs were evolving in the various organizations led me to an interesting epiphany related to the application of Gall’s Law to system design. Gall's Law is a rule of thumb from John Gall's Systemantics: How Systems Really Work and How They Fail: “A complex system ... » read more

Good Times, Good People
By Atrenta - 31 Mar, 2011 - Comments: 0

I lost a long-time friend this past week. He was a member of the EDA community and so I will dedicate this blog to a discussion of the late Dr. Aaron Ashkinazy—the person, his contributions and the process for his work. The person. Aaron had a lot of friends. We’ve all been reminiscing about him this past week and some consistent comments arise. He was one of the most intelligent and kin... » read more

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