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Author's Latest Posts


New Product Introduction Process For Heterogeneous 2.5D Devices


For the past few years, the most popular topics in the 2.5D space have been: The design tools Foundry processes for through-silicon vias, temporary bonding and bump architecture The assembly process, such as what is first bonded to what The industry is at the point where the open variables on these topics are narrowing, and other critical aspects need to get far better attention. The... » read more

Stacking The Deck


By Javier DeLaCruz The pinnacle of system-on-chip has passed. There are several dynamics that are moving the industry away from the SoC philosophy that was so popular just a few short years ago. One of the significant factors is that the cost per gate for CMOS nodes below 28nm is rising for the first time in the history of our industry. Another critical factor is the emergence of through-silic... » read more

Stacking The Deck


By Javier DeLaCruz The pinnacle of system-on-chip has passed. There are several dynamics that are moving the industry away from the SoC philosophy that was so popular just a few short years ago. One of the significant factors is that the cost per gate for CMOS nodes below 28nm is rising for the first time in the history of our industry. Another critical factor is the emergence of through-silic... » read more

The New ASIC


By Javier DeLaCruz The current state of the art For years, large ASICs like the ones used in network processing, supercomputing and high-end personal computing have had very interesting similarities. The figure below is a fairly typical floorplan of such an ASIC. After taping out over a dozen of these types of chips a year, it is interesting to see that the interfaces have changed, processo... » read more

When Stacked Die Make Sense


By Javier DeLaCruz There are two general flavors of 3D-TSV technology. Images for these can be seen in the previous blog entry The Future of ASICs in 3D. 3D-IC has vias in silicon containing active circuitry. 2.5D is similar, but uses passive silicon, glass or organic interposers to enable very fine pitch interconnection between the active die mounted on top. There is some discussion about ... » read more

The Future Of ASICS In 3D


By Javier DeLaCruz 3D technology is generating a lot of interest as a way to reduce NRE costs and speed time to market. This is still a nascent approach, so people are looking for a single standard in through-silicon vias (TSVs), primarily to reduce infrastructure costs. Unfortunately, I do not think this will be possible. There are at least two fundamentally different applications for 3D t... » read more

The Current State Of 3D Stacking


By Javier DeLaCruz Thru-silicon-vias (TSVs) have become a very hot topic in in recent months. Ever since Xilinx reported that it is using a 2.5D TSV approach for its Virtex-7 FPGAs the industry started to salivate with the prospects of this new technology. While this technology may be accessible for larger stacked memory, FPGAs, MEMS devices, and CMOS image sensors, this does not inherently me... » read more

The Turning Point


By Javier DeLaCruz In the epic battle of cost and performance, MCMs (multi-chip modules) had generally lost to SoCs (systems on chip) due to higher package-assembly costs and lower performance. The tides are turning. Four factors have been in play in recently: Package assembly costs of MCMs have been dropping in recent years. MCM package technologies are becoming commonplace instead... » read more

What’s the cheapest package that will work?


By Javier DeLaCruz, So often, I come across questions from customers asking what’s the lowest cost package technology that will work. The package by itself should not be the singular focus when considering the lowest-cost solution for a new ASIC. The best approach is to take a few steps back and consider the system and what would work best for that given system, from a variety of standpoint... » read more

What’s With That Big Package?


By Javier DeLaCruz As SerDes data rates have been going up for years, and 10-Gbps interfaces have been becoming commonplace, I figured a few years ago that pin counts on packages would start going down. Boy, was I wrong on that prediction! The trend instead was to put more of those high-speed interfaces on devices. For years, a 45×45mm body size was really the upper limit on organic f... » read more

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