The Future Of ASICS In 3D

As stacking of die comes into focus it looks as if the approach will be to use layers of tiles as building blocks.


By Javier DeLaCruz
3D technology is generating a lot of interest as a way to reduce NRE costs and speed time to market. This is still a nascent approach, so people are looking for a single standard in through-silicon vias (TSVs), primarily to reduce infrastructure costs. Unfortunately, I do not think this will be possible.

There are at least two fundamentally different applications for 3D technology that are driven by completely different incentives. The mobile space is driven mostly by the need for reduced power, height and area. The infrastructure and networking space is driven by the need for yield improvement and the ability to insert more memory than is monolithically possible—at much lower power. Mobile devices need thin architectures and very thin packages. On the other hand, larger networking devices require thicker 3D ICs or interposers to handle the flatness needed for larger die and the side-by-side architectures of the devices.

These are really exciting times: 3D and 2.5D technology could change the entire landscape and architecture of ASICs. This already has started in FPGAs and ASSPs, but ASICs face a particular challenge. ASICs do not generally have the benefit of high volume required to secure sources, influence foundries, and gain early access to 3D technology—which they need if they want to be in a leadership role in this implementation.

The exponentially rising cost of tapeouts at lower nodes has resulted in fewer tapeouts at these emerging technologies. As a result there are fewer experts in this field. Some companies will be able to spend a lot of money developing the technology and hence developing the expertise in the field. The rest of us will have to rely on strategic partnerships to help and hand-hold as we cross the threshold into this technology.

Fig. 1: A basic 2.5D structure.

Foundries and assembly houses are keeping their 3D-IC cards close to vest and waiting for industry leadership to come from the users of 2.5D and 3D technology. Obviously, they do not want to spend all that money to find out later that they need to change course to follow the prevailing current.

eSilicon has spent a good amount of time and effort on 3D- and 2.5D-IC technology. We believe that ASICs will need what we are referring to as a menu for “tiles,” such as memories, microprocessor subsystems, integrated passive devices, FPGA die, and other devices. In that model tiles are proven building blocks. A 2.5D or 3D-IC implementation could include tiles in leading-edge technologies like 28nm, with a lower NRE thanks to a 65nm-based interposer. The proven tiles mean the design team doesn’t have to re-invent the wheel, saving time and reducing risk.

Fig. 2: An example of a 3D IC.

We—along with our partners—certainly want to take a leadership role in the 3D-IC space. At the same time, we need to understand where the prevailing currents are flowing. I do not think any of us will have all the answers, but ongoing conversations with partners and customers are getting us closer to understanding where the need is. Once you know where the need is, the direction will become abundantly clear.

–Javier DeLaCruz is eSilicon’s semiconductor packaging director.

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