What’s With That Big Package?

Thermal estimates aren’t always accurate at first, so expect the worst.


By Javier DeLaCruz
As SerDes data rates have been going up for years, and 10-Gbps interfaces have been becoming commonplace, I figured a few years ago that pin counts on packages would start going down. Boy, was I wrong on that prediction! The trend instead was to put more of those high-speed interfaces on devices.


For years, a 45×45mm body size was really the upper limit on organic flipchip packages (HFCBGA). The reason for this was the curvature of the package laminate that occurred due to the thermal expansion mismatch between the silicon (2.5ppm/°C) and the substrate (17ppm/°C). As the package grew, this curvature caused a flatness problem for the field of solderballs on the package.

This spec is referred to as coplanarity and is governed by JEDEC standards. For these larger packages, the spec for coplanarity is 0.2mm. This is a very important and seldom discussed dimension in larger packages because it will determine whether or not a part will be solderable to a PCB. Generally this number is pretty conservative, and it needs to be because JEDEC does not know the thickness of the solder stencil that will be used at PCB assembly. A thick stencil means a thicker deposit of solder will be made on the PCB at assembly, which would accommodate a more warped package. This ignores the fact that as parts reach solder-melt temperatures, they tend to flatten out again since this high temperature is a much lower stress condition for a package in general. The “ddd” dimension in the dimensioned image shows how this coplanarity dimension is specified.

Ceramics had always been a solution to maintaining acceptable flatness for larger devices, but the inordinately high cost made this tradeoff difficult to swallow. Stiffener rings also have been used, but they are difficult to manage on a laminate prior to flipchip assembly, and are only usable on more expensive assembly lines. Lower-cost flipchip assembly subcontractors do not use devices with stiffener rings, given that they do not fit well into their assembly processes.

Several recent events have broadened the horizon for organic flipchip packages. There are now newer package dielectric materials that have a lower thermal expansion rate. This makes a part warp less after flipchip attach reflow. Another key point is that some assembly houses are using much thicker heat spreaders to re-flatten a package and keep it flatter. This seems to have opened the door to flipchip packages up to the 55×55mm range.

As the available size of a package grows and the interfaces continue to utilize more high-speed SerDes, you just can’t ignore the 800-pound gorilla in the room, heat dissipation! Pulling the heat out of these devices is rapidly becoming a bottleneck in this trend. The cost of pulling the heat out of these devices has been an afterthought, but really needs to be considered up front when planning for a device. Thermal estimates are not always accurate early on, so planning for a worst-case scenario may be prudent.

–Javier DeLaCruz is eSilicon’s semiconductor packaging director.

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