When Stacked Die Make Sense

By Javier DeLaCruz
There are two general flavors of 3D-TSV technology. Images for these can be seen in the previous blog entry The Future of ASICs in 3D.

3D-IC has vias in silicon containing active circuitry. 2.5D is similar, but uses passive silicon, glass or organic interposers to enable very fine pitch interconnection between the active die mounted on top. There is some discussion about adding some basic active circuitry to these silicon carriers to enable better testability, but that is for a different blog entry. If glass or organic interposers are used, it is possible that this may not even include a TSV, but for simplicity in this entry we’ll just assume it does have TSVs.

These simple descriptions do not cover all flavors as simply as chocolate and vanilla. There are also several combinations like “rocky road” that combine elements of each and introduce other ingredients. Much like consumers of ice cream that gravitate to certain flavors, so are the types of companies that will utilize each of these technology flavors, and for very good reasons.

Who will use 3D-IC?
ASIC 3D-IC implementations will be driven by several key market drivers. 3D-IC offers the promise of considerable miniaturization. The stacking of die that would otherwise be adjacent to each other reduces the area required on a PCB. While both 3D-IC and 2.5D technologies reduce PCB real estate, 3D-IC has the promise of having a greater real estate reduction.

There is also the promise of lower power consumption when communicating with ASICs or ASSPs. Signals do not need to be driven at higher voltages since the IR (current X resistance) drop from die vertically stacked is minimal, so the IO may just need to operate at the same voltage as the core of the die. In fact, the miniaturization must be coupled with lower power solutions or else these compact devices will overheat. Heat is the biggest problem with 3D-IC, so this will likely be restricted to low-power devices, or solutions that can have inordinately expensive heat-sinking solutions, such as supercomputers.

There is also a cost premium to this solution, as it would be less expensive to design these active die as a monolithic ASIC, or different MCM (multi-chip module) solution. The users for this will be those willing to pay a premium for this smaller, lower-power option. Hence, the main users for this will be mobile devices. A smaller phone with a longer battery life is worth more to the end consumer, so the mobile component manufactures can justify this premium. The lower power usage in this space is also a great fit for this technology.

Who will choose a scoop of the 2.5D flavor?
2.5D technology doesn’t really save a lot of space. It still has some benefit of power reduction, although you still need to drive many millimeters (instead of many inches) across an interposer. Here the benefits of partitioning, re-use and mixing technology will dominate.

Partitioning is the ability to separate various portions of an ASIC into separate die. This would include a CPU, embedded memory, SerDes, etc. The partitioning would enable:

1. Better yields due to smaller die;
2. The ability to re-use these “tiles” of partitioned silicon in future designs, and
3. Elimination of the reticle limit governing die sizes. (The area sum of several large tiles on a silicon interposer may exceed what would have otherwise been possible on a single monolithic die due to the size limit of the reticle.)

The most strategic approach to 2.5D technology is the ability to mix silicon technologies such as SiGe, DRAM, RFCMOS or silicon of various nodes such as 28nm and 130nm on the same interposer. This ties back to the re-use benefit mentioned earlier. If a CPU tile is taped out at 28nm and proven, it can be re-used across multiple designs.

Ask yourself what drives you to shrinking silicon wafer nodes? It is generally an area, power efficiency or speed limitation for one or two silicon IPs on your die. The logic on your ASIC may not likely benefit much from the smallest node available. Therefore, produce tiles for the aggressive IPs such as the CPU or SerDes in an advanced silicon node such as 28nm. Then use a legacy node for the logic, which would bring down the overall risk and cost of a system. If the advanced tiles can be re-used, then only the legacy-node logic tiles would need to be released for future generations, which would reduce the cost associated with new devices.

Let’s say your next-generation device requires two CPUs, then just put a second CPU tile on your interposer. There would be no additional risk since this tile would be proven and reused from a previous design. There is more area associated with this approach, but the benefits are very compelling. The products that would benefit the most from a 2.5D strategy are the more power-intensive enterprise-level systems such as network processors, large FPGAs, non-mobile CPU applications, etc.

–Javier DeLaCruz is the manufacturing technology director at eSilicon.