April 2011 - Page 3 of 5 - Semiconductor Engineering

Power Changes Everything
By Ed Sperling - 14 Apr, 2011 - Comments: 0

By Ann Steffora Mutschler Optimizing design methodologies for effective power utilization sometimes meaning throwing out old ideas and approaches and starting fresh. This is exactly what wireless chip giant Broadcom did in its quest to manage power in its chips. Low-Power Engineering spoke with Michael Hurlston, vice president of the mobile wireless group at Broadcom, to discuss current and f... » read more

High Performance And Low Power
By Ed Sperling - 14 Apr, 2011 - Comments: 0

By Pallab Chatterjee As mobile platforms become a larger part of the component spectrum, their need for optimization beyond low power has moved to the forefront. Traditionally, standard "line-cord" based products in both the consumer and commercial sectors have used the "G" label processes from semiconductor foundries. These processes had the highest-yielding combination of design rules, d... » read more

Power Issues In 3D
By Ed Sperling - 14 Apr, 2011 - Comments: 0

By Ann Steffora Mutschler The challenges associated with implementing IP subsystems range from maintaining a consistent I/O voltage, achieving consistency in metal stacks to managing a clock distribution network and creating adequate isolation between subsystems on a chip. It’s enough to make your brain hurt. Add to that 3D or 2.5D stacking and the engineering considerations grow substantial... » read more

Rationalization For Power
By Ed Sperling - 14 Apr, 2011 - Comments: 0

By Ed Sperling Power budgets are becoming almost universally problematic. What used to be a unique headache for the cell-phone market has evolved into an ugly migraine that now includes everything with a battery—and increasingly even those devices that rely on a plug. The result is a cascade of effects that are widespread and growing. And while the drivers of this effort vary widely from ... » read more

Power Budgeting 101
By Aveek Sarkar - 14 Apr, 2011 - Comments: 0

By Aveek Sarkar With all the processing power that is being designed into smart and superphones now, I wonder what would happen if all four multi-GHz processors were to execute simultaneously? How long would that small battery last—and would anyone be able to hold it in their bare hands?   [caption id="attachment_6305" align="alignnone" width="342"] Phone surface temperature as a ... » read more

Advanced Modeling Technologies For Chip, Package, System Co-Analysis And Co-Optimization
By Various Writers - 14 Apr, 2011 - Comments: 0

The traditional approach to chip-package-system (CPS) co-analysis and co-optimization lacks required accuracy and limits productivity. To meet the increasing demands for system cost down calls for a new methodology that is more comprehensive. This white paper outlines the Chip Power Model (CPMT) technologies and solutions available from Apache Design Solutions to help address the CPS convergenc... » read more

RTL Power Estimation
By Luke Lang - 14 Apr, 2011 - Comments: 0

By Luke Lang A few months ago, I wrote about power estimation—finding the worst-case toggle rate to determine the worst-case power. This has been used very successfully by many designers to get an accurate estimation and analysis of power dissipation. These designers also are using the worst-case toggle rate to optimize power grid and meet dynamic IR drop requirements. With these power estim... » read more

Emulation Power
By Barry Pangrle - 14 Apr, 2011 - Comments: 0

By Barry Pangrle Power budgets and the characteristics of the underlying process technologies have limited the clock speeds of the processors often found in large compute farms for simulation over the past six years, but the designs under test have followed Moore’s Law and have kept growing larger at an exponential rate. Processor designers have added more cores per chip to increase the p... » read more

Fire In The Hole?
By Bhanu Kapoor - 14 Apr, 2011 - Comments: 0

By Bhanu Kapoor At the 2001 ISSCC, Pat Gelsinger, then Senior VP at Intel, had observed the following in connection with the growing issue of chip power density: “Ten years from now microprocessors will run at 10GHz to 30GHz and be capable of processing 1 trillion operations per second—about the same number of calculations that the world's fastest supercomputer can perform now. Unfortunate... » read more

The Power Blues
By Ed Sperling - 14 Apr, 2011 - Comments: 0

When it comes to power in SoC designs, most engineers will agree that the easy stuff is already done. What’s interesting, though, is they’ve been saying that for several process nodes, and the complaint has been roughly the same no matter what node they’re actually working at. It’s as true today for engineers working at 180nm with analog chips as at 28nm with the latest digital process ... » read more

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