Power Changes Everything

User Perspective: Creating low-power ICs at Broadcom has required some radical rethinking of the flows and how technology is applied; leakage challenge grows.


By Ann Steffora Mutschler
Optimizing design methodologies for effective power utilization sometimes meaning throwing out old ideas and approaches and starting fresh. This is exactly what wireless chip giant Broadcom did in its quest to manage power in its chips. Low-Power Engineering spoke with Michael Hurlston, vice president of the mobile wireless group at Broadcom, to discuss current and future power challenges.

LPE: What are some of the business challenges of developing new low-power designs?
Hurlston: Wireless LAN chips originally were designed for applications like notebook computers, home routers and home gateways. In those particular applications, power was not so much a concern—maybe in notebooks a little bit—but I would say that the majority of questions we were getting from our customers had nothing to do with power consumption. Then in 2007 we got the crazy idea that maybe we could put Wi-Fi technology into ultra-portable applications like cell phones, portable games, iPods—things that were really battery-sensitive. As a result, obviously a focus from our customers was going to be on power. We had to at that time change our whole design philosophy to really focus on power. We ripped out our entire design methodology at that time and re-did it with a central theme of how do we get this power consumption out. There are a number of different aspects to power consumption. For a wireless chip there’s power while you are just sitting there in an idle state. There’s power when you’re transmitting or receiving—when you are actually active. And then there’s power that’s somewhere in the middle where you are kind of operating but you are really not. We had to optimize all three kinds of power consumption and rip out our entire design flow to refocus on power. That became a big challenge for us. In a wireless technology it’s all about balancing those demands: idle/leakage demand, active demands and then the quasi-on state, which we call sleep mode.

LPE: Specifically what did you change about your design flow?
Hurlston: A couple of key things changed that were very significant. In the old topology we had basically one power plane, which means that everything was operating off of sort of a universal power supply. One of the key architectural advancements we made was to do power islands and focus on things that were going to be ‘on’ at the same time by virtue of their operation. So rather than having one supply that is essentially running the whole chip we now have dozens. And each of the different power supplies is feeding a different part of the integrated circuit, and that power supply can then be turned on or off depending on whether that particular portion of the circuit is going to be needed for whatever operation is at hand. That was one thing. The second thing was to carefully architect the design to gate clocks going to areas that were non-essential for that particular operation. So rather than having the clocks indiscriminately fan out on the chip and then be running and toggling all the time we shut off clocks going to one portion of the chip or another. And the third advancement most specific to wireless LAN technology was bringing power amplifiers onto the chip. Any wireless technology needs some kind of power amplifier. Before that we were funneling our signaling off chip to an external power amplifier that we had very little control over. By bringing the power amplifier on chip we were designing in CMOS technology, which is a lower power technology than the BiCMOS or silicon germanium that was used for our external power amplifiers. We also were able to bring a tighter control loop between the power amplifier and the rest of the circuit, which allowed us to do some intelligent monitoring of the power amplifier and increase or decrease its output power. Obviously as you’re increasing the output power you’re increasing the power draw. We were able to create a feedback loop. Bringing those power amplifiers on chip was a very big benefit for us. We were the first company to be able to do that, and now it’s fairly pervasive in Wi-Fi technology.

LPE: Which foundries do you work with?
Hurlston: We have designs that are portable among four partners that we talk publicly about: SMIC, TSMC, Global Foundries and UMC. We feel like we are relatively unique where we can do one tapeout that is portable among those foundry partners and, depending on loading conditions in the fab, the pricing in a particular fab and a number of different factors we’ll ultimately steer a chip tapeout to one of those four. In certain cases, we’ll multi-source it where we will run the same device at two or more of those foundries.

LPE: What process geometry are your products manufactured with today?
Hurlston: Most of our products are at 65nm. We’ve announced as a company that we’re aggressively embarking on 40nm and that’s been a companywide shift toward 40nm. We are still shipping some of our older products in 130nm.

LPE: Do you ever run into issues with a single design between foundries?
Hurlston: Very, very rarely. It’s probably not fair of me to say, ‘none.’ You have to remember we are the largest tenant at three of those four foundries and among the top three at the fourth. So we definitely have the ability to get these guys to do some of the work for us. We have to do some of the work ourselves and try to come up with a common set of libraries and a common set of models that work across all of the foundries, but they are equally motivated to work with us. The goal is that our customers can have a board that would accept silicon from any one of those foundry sources.

LPE: When embarking on a new design, how much IP is being re-used?
Hurlston: Broadcom is interesting in that regard. We have a multi-layer model where first, we have centralized engineering—a central engineering team—and that central engineering team actually does things like phase-lock loops, analog-to-digital converters and power supply types of circuits. There are a whole host of things that they do and then farm out to all of the different chips that get done within Broadcom. All of the different businesses within Broadcom are drawing from that central engineering team and that gives us a tremendous amount of re-use. Even a wireless LAN block that my team is responsible for, we make it so it is portable among other chips so in the event that another business unit wanted to incorporate the wireless LAN function in a larger chip, they can very easily take our wireless LAN block and marry it to a larger system chip that they might be doing. We recently announced a chip like that where we took a DSL engine and it had a wireless LAN block inside. Our whole company is built up on IP re-use.

LPE: Looking ahead, what are the biggest technical challenges going to be in terms of developing for low power?
Hurlston: Obviously we are getting to a point where there are tradeoffs between lower and lower process geometry and leakage. I think the biggest thing that we get into now is standby power, which is somewhat inversely proportional to process geometry. Active power is directly proportional to process geometry, standby power is somewhat inversely proportional. In other words, as we go down in process node the leakage current goes up without a lot of extra precautions being taken. I would say that is the singular biggest challenge is how to solve this leakage problem.

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