July 2011 - Page 2 of 5 - Semiconductor Engineering

Start The Revolution
By Jon McDonald - 28 Jul, 2011 - Comments: 0

By Jon McDonald “Know thyself.” That advice is promoted in so many different forms it's hard to know where it started. I have been involved in a number of projects recently in which these words would have greatly simplified the project flow. “Simplified” is probably not quite the right word. The issue in this case is not to simplify the project, but to properly understand, characterize... » read more

The Evil Doctor
By Atrenta - 28 Jul, 2011 - Comments: 0

I’ve always been a fan of superhero movies. I would say the Terminator series is the last time I really liked Arnold Schwarzenegger. I bet I’m not alone in that opinion. I think it’s terrific when downtrodden bands of X-Men use their strange powers to defeat evil. The summer blockbuster season is in full swing with movies like Green Lantern and Captain America. A good time will be had ... » read more

Understanding Formal Verification Concepts, Part II
By Various Writers - 28 Jul, 2011 - Comments: 0

In this second white paper in a three-part series about formal verification concepts, we examine the assertion-based verification flow and some of the formal verification algorithms. This kind of approach has become necessary as SoC designs become more challenging and as the traditional method of simulation proves too slow, too costly, and insufficient in terms of coverage. To downoload thi... » read more

Debugging Double Patterning without Getting Double Vision
By David Abercrombie - 27 Jul, 2011 - Comments: 1

By David Abercrombie Given that my last couple of blogs on double patterning (DP) might have scared you to death, I figured it was time to bring you some good news. It is unavoidably true that double patterning layout constraints at 20nm and below are going to require changes in all aspects of the design flow, but Mentor Graphics (and, I am sure, the rest of the EDA industry) is working very... » read more

Experts At The Table: Multi-Foundry Strategies
By Ed Sperling - 26 Jul, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing and Design sat down with Walter Ng, vice president of the IP ecosystem at GlobalFoundries; John Murphy, director of strategic alliances marketing at Cadence; Michael Buehler-Garcia, director of Calibre design solutions marketing at Mentor Graphics; Bob Smith, vice president of marketing and business development at Magma, and Linh Hong, vice president ... » read more

Is EUV the SST of Lithography?
By Chris Mack - 26 Jul, 2011 - Comments: 0

Analogies with Moore’s Law abound. Virtually any trend looks linear on a log-linear plot if the time period is short enough. Some people hopefully compare their industry’s recent history to Moore’s Law, wishfully predicting future success with the air of inevitability that is usually attached to Moore’s Law. Others look to some past trend in the hopes of understanding the future of M... » read more

For want of an o-ring, the mask was lost
By Katherine Derbyshire - 25 Jul, 2011 - Comments: 0

O-ring seals are everywhere in a typical semiconductor fab. Any piece of vacuum equipment uses several of them to seal the openings where components of the process chamber fit together. Yet, as ubiquitous as they are, most process engineers don’t think about them very much. They buy the seal specified by the equipment vendor, from the supplier with the most attractive price, and pretty much l... » read more

The Big Picture
By Ed Sperling - 22 Jul, 2011 - Comments: 0

Business is booming for the makers of processors. Intel posted its five consecutive record quarter, AMD turned a profit, Tensilica shipped its billionth DSP, ARM and MIPS are both reporting strong earnings. So what’s changed? There are several distinct trends driving this upbeat mood: The replacement cycle. After years of putting off purchases through a prolonged and deep downturn, com... » read more

Extending Battery Life
By Ed Sperling - 21 Jul, 2011 - Comments: 0

By Ed Sperling In the past it was all about clock frequency. People bought the latest computer and frequently paid a premium because it could crunch numbers faster. But as computing moves from the desktop into handheld devices, that focus is radically changing. Low-Power Engineering caught up with Mark Bohr, senior fellow and director of Intel’s process architecture and integration, to ta... » read more

Low Power: Coming To A CE Device Near You
By Ed Sperling - 21 Jul, 2011 - Comments: 0

By Pallab Chatterjee Low power and connectivity are the two pervasive design constraints for chips and systems being designed today, and they are showing up in devices that have not had architectural changes in decades. Some of the changes are customer-driven, some are consortia-driven, and international cooperation is making some of the regulatory-driven. The regulatory side is moving slow... » read more

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