July 2011 - Page 3 of 5 - Semiconductor Engineering

Design For Power Methodology
By Ed Sperling - 21 Jul, 2011 - Comments: 0

By Ann Steffora Mutschler It is rare to find an advanced chip today that has not been designed considering power from the very earliest point. In fact, it is safe to say that power is the No. 1 priority, or a close No. 2. But to achieve the highest performance for a low-power design, a design-for-power methodology is necessary, comprised of the capabilities to implement power in the most ef... » read more

Customer perspective: STMicroelectronics
By Ed Sperling - 21 Jul, 2011 - Comments: 0

By Ann Mutschler With eight SoC designs currently in development on its 28nm manufacturing process, STMicroelectronics is well acquainted with the power challenges of making those designs work. LPE discussed these issues with Philippe Magarshack, ST’s Technology R&D Group Vice-President. What follows are excerpts of that conversation. LPE: What are the biggest challenges in getting ST... » read more

Top 5 Reasons For Power Consumption Waste
By William Ruby - 21 Jul, 2011 - Comments: 0

By William Ruby Low-power seems to be on everyone’s mind these days, and it’s not just the chip design teams. One common consumer complaint is that the “battery life is way too short”! And of course, we all know this one, “OMG – that laptop is sure hot“! Even data center facilities managers lament, “We can’t supply enough power to the equipment—and when we do, we can’t co... » read more

RTL Design For Power Methodology
By Various Writers - 21 Jul, 2011 - Comments: 0

This power budgeting white paper presents a design-for-power methodology, starting early in the design process at the Register Transfer Level (RTL), to help deliver maximum impact on power. To download this white paper, click here. » read more

Hierarchical LP Design
By Luke Lang - 21 Jul, 2011 - Comments: 0

By Luke Lang The rapidly shrinking process geometry is a double-edged sword. It allows unprecedented integration of circuits. But it also produces leakier transistors, which is one of the main reasons behind the need for low-power design techniques. Therefore, a good low-power design flow must not only automate low-power design, verification, and implementation, it must also support hierarchic... » read more

Building A Better CMOS FET
By Barry Pangrle - 21 Jul, 2011 - Comments: 0

By Barry Pangrle SEMICON West was held last week in San Francisco and I had the opportunity to attend the Emerging Architectures session. Serge Biesemans, vice president of process technology at Imec, gave a nice overview presentation on FinFETs. From a power and performance standpoint, we’ve seen some early pre-production information released from Intel that I briefly discussed here. Serge�... » read more

Viewing Power Through A Funnel
By Ed Sperling - 21 Jul, 2011 - Comments: 0

If Moore’s Law had a corresponding geometric shape, it would be a funnel. At older nodes, the wider part of the funnel could accommodate a full SoC or ASIC. At advanced nodes, moving further into the funnel, only portions of an SoC will actually be designed and built—mostly the digital logic and memory. Everything from analog portions to standard IP and even non-standard IP will be construc... » read more

Experts At The Table: Multi-Core And Many-Core
By Ed Sperling - 21 Jul, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down with Naveed Sherwani, CEO of Open-Silicon; Amit Rohatgi, principal mobile architect at MIPS; Grant Martin, chief scientist at Tensilica; Bill Neifert, CTO at Carbon Design Systems; and Kevin McDermott, director of market development for ARM’s System Design Division. What follows are excerpts of that conversation. LPE: Computers aren’t gettin... » read more

Aren’t We Beyond That?
By Ann Mutschler - 21 Jul, 2011 - Comments: 0

The latest and greatest technologies always get the most attention because they are new and fresh, but gate-level simulation—a long-time workhorse tool—is seeing a small comeback with designers as of late. According to Cadence’s Pete Hardee, even though the industry is spending a lot of time looking ahead to architectural-level power modeling and virtual prototyping, the need for detai... » read more

Blog Review: July 20
By Ed Sperling - 20 Jul, 2011 - Comments: 0

By Ed Sperling Synopsys’ Eric Huang pays a visit to the Microsoft Store and finds a really smart salesperson who seems to know just about everything there is to know about the products for sale. And yes, that is somewhat unexpected. Cadence’s Jean-Michel Fernandez talks about creating SystemC peripheral models. Fernandez represents Cadence’s Team ESL, which is an interesting developme... » read more

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