Viewing Power Through A Funnel

Visualizing the problem doesn’t make it easier to solve, but it does help understand how daunting it will be.

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If Moore’s Law had a corresponding geometric shape, it would be a funnel. At older nodes, the wider part of the funnel could accommodate a full SoC or ASIC. At advanced nodes, moving further into the funnel, only portions of an SoC will actually be designed and built—mostly the digital logic and memory. Everything from analog portions to standard IP and even non-standard IP will be constructed at whatever node has already been proven, which is the wide part of the funnel.

This has significant ramifications for power in 2D configurations. It means that power budgets need to be calculated based upon what’s going into a chip at the architectural level, with the same considerations given to all of the derivative chips that will spring from an initial design. Techniques such as power gating, power islands, and using multiple voltages, when designed in up front, could affect several years worth of derivative chips. That means if it’s done wrong in the first place it will have unhappy consequences for years to come.

But in a market where 70% of the content is re-used—and in some cases up to 90%—that implies a combination of electrical properties such as voltages and leakage. Building chips that use various combinations from throughout the funnel will make it harder to fit into a defined power budget. In the past, that was somewhat optional. Energy efficiency has become a competitive requirement, along with time to market. That means pieces of a design will have to come from all parts of the funnel, but they also will have to fit into a power budget close to those designs at the narrowest part.

In 2.5D and 3D stacks, this will get even more interesting because the power budget of a stack isn’t even the same as the power budget for individual die. It’s uncertain, in fact, how budgets will change because it will vary according to thermal dissipation. Some die may actually conduct heat away from the chip, while others will simply cook it into oblivion.

Geometry and electrons have always shared an uneasy partnership, which is one of the challenges of layouts and interconnects. But that relationship is about to take on some new dimensions as we move forward to the next couple of process nodes.


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