September 2011 - Page 2 of 4 - Semiconductor Engineering

More Intelligent Verification
By Jon McDonald - 22 Sep, 2011 - Comments: 0

By Jon McDonald If I have flipped a coin 1,000 times and it's come up heads every time what are the odds that I will get another head on the next flip? The odds on the next flip are still 50/50. The fact that I observe a uniquely unlikely situation has no impact on my current probability, and frankly any sequence of prior results would be equally unlikely. I find some of the same thinking appl... » read more

What A Difference A Decade Makes
By Tiffany Sparks - 22 Sep, 2011 - Comments: 0

By Tiffany Sparks Lately, I find myself in a reflective mood, pondering what’s changed over the past 10 years. Of course, with the 10th anniversary of 9/11 earlier this month, there’s been intense focus on what the world was like 10 years ago and what has changed since that fateful day: the thousands of lives lost, first on 9/11, then the lives lost in Afghanistan and Iraq; the geo-poli... » read more

Finer Control, Same Ideas
By Ed Sperling - 22 Sep, 2011 - Comments: 0

Famed lawyer Clarence Darrow once said, “History repeats itself, and that’s one of the things wrong with history.” While that basic theme has been argued throughout the history of civilization—smart people are supposed to learn from other people’s mistakes, not just their own—there's an interesting twist when it comes system-level design. We are using the same technological appro... » read more

Executive Briefing: 3D IC Stacking Challenges
By Ed Sperling - 21 Sep, 2011 - Comments: 0

Sonics CEO Grant Pierce sounds off on the challenges of stacking die, what has to change and why. [youtube vid=wCseVs738LQ] » read more

IEEE Photonics or LEOS conference preview
By Michael Watts - 20 Sep, 2011 - Comments: 0

By Michael Watts “Visualizing stem cells in 3D”, perhaps from Peyton Manning or Dick Cheney, is a paper that actually connects to the headlines. University of Maryland researchers will detail a non-destructive imaging technology they have developed to enable better three-dimensional viewing of fluorescent-labeled stem cells within a tissue scaffold. The existing alternative uses cryogeni... » read more

DFT: Essential For Power-Aware Test
By Ed Sperling - 18 Sep, 2011 - Comments: 0

By Ann Steffora Mutschler Power-aware test is a major manufacturing consideration due to the problems of increased power dissipation in various test modes, as well as test implications that come up with the usage of various low-power design technologies. Challenges for test engineers and test tool developers include understanding the various concerns associated with power-aware test, develo... » read more

Experts At The Table: Retrofitting Older Process Nodes
By Ed Sperling - 16 Sep, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down with Walter Ng, vice president of the IP ecosystem at GlobalFoundries; Vishal Kapoor, vice president of marketing for SoC realization at Cadence; Naveed Sherwani, CEO of Open-Silicon; John Heinlein, vice president of marketing at ARM; and Jeff Lukanc, director of engineering at IDT. What follows are excerpts of that conversation, which was held in... » read more

A Different Kind Of Design
By Ed Sperling - 16 Sep, 2011 - Comments: 0

Intel’s announcements at the Intel Developer Forum this week that it will be creating physically smaller packages that can run on far less energy raises some interesting questions about the future of all design. We’ve become accustomed to one-chip implementations, whether that’s a monolithic processor or an SoC with lots of processors. In the future, though, there may be multiple chips, a... » read more

Multi-Patterning: Game Changer or Y2K?
By Mentor Graphics Staff Writers - 14 Sep, 2011 - Comments: 0

By Joe Davis, Mentor Graphics Every new technology node brings new process challenges that translate into design challenges. For the last five years, design rules and processes have had to deal with an increasing impact from nearest-neighbor and environmental effects from lithography, stress, and temperature. Where once cells could be designed and placed independently, now a cell’s real pe... » read more

450mm and EUV Linked With Uncertainty
By Jonathan Davis - 13 Sep, 2011 - Comments: 0

By Jonathan Davis The transition to manufacturing semiconductors on larger wafers continues to be one of the hottest topics in the industry. Some chipmakers have committed to advancing the transition. Intel announced that its D1X fab in Oregon will be 450mm compatible (2013). TSMC announced a 450mm pilot line by 2013-2014. IMEC and ISMI have well-established programs focused on the challeng... » read more

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