DFT: Essential For Power-Aware Test

DFT architecture needs to be aligned with power management strategies; but how accurate are the tests and do they lead to over-design?

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By Ann Steffora Mutschler
Power-aware test is a major manufacturing consideration due to the problems of increased power dissipation in various test modes, as well as test implications that come up with the usage of various low-power design technologies.

Challenges for test engineers and test tool developers include understanding the various concerns associated with power-aware test, development of power-aware design-for-test (DFT), automatic test pattern generation (ATPG) techniques, test power analysis flows, among other issues.

“Power is one of those key drivers in what we’re building today, especially in mobile applications,” said Savita Banerjee, SoC test and verification manager at LSI. “In the past speed, area and cost were the big-ticket items, but power has really come into play.”

Banerjee: Power has really come into play in designs.

Her team specifically works with storage customers where power, cost and performance are all critical. “The two important aspects of power-aware test for us are related to the actual DFT implementation and the impact it has on yield,” she said. “Typically, the SoCs that we are developing have a power architecture and are designing power into what they are building so they can get additional power savings rather than just reducing power supplies and skewing parts and things. They actually have very comprehensive power architectures that allow them to get more power savings than they normally would have if they hadn’t built that into the design.”

From a test angle, it’s important for the DFT architecture to actually align with those power management strategies, Banerjee stressed. “DFT is not really sitting on the sidelines now. It really has to integrate well with the overall design solution. It’s important that when you define a test strategy and a test architecture, you need to make sure you are implementing those DFT structures in such a way that you consider the power architecture and the power needs of that application.”

In the past, this was a manual process, she said. LSI has chosen to work with Synopsys to implement DFT and leverage power-aware constructs. “The most important thing is how power intent is specified and how that gets carried forward in the DFT implementation process.”

She noted that when LSI first engaged with Synopsys more than a year and a half ago, the flow that was advertised out of the box didn’t work as expected. “We spent a good year working very closely with them to help mature the flow and really define what our requirements were and come up with a flow that was a lot more seamless. I think it was one of those examples where the EDA vendors do need to partner with actual users of their tools to be able to deliver what’s needed.”

The intersection of power and test
Power and test intersect in a number of areas. First, DFT must respect the power intent. “When someone puts test into their design, they want to make sure that if it is a low-power design it doesn’t break the low power,” explained Robert Ruiz, senior product marketing manager for test automation products at Synopsys. “As we consider designs that are developed for low power there are often multiple voltage domains and power domains, and the DFT has to be cognizant of that now. In the old days, it was just taking the flip-flops, converting those to scan flops, hooking those up and everything worked well. That can’t be done so easily now.”

As an example, when a scan chain crosses from one voltage domain to another, a level shifter has to be put in. That task becomes even more complex because if the tool just blindly puts in level shifters it will cause to be a huge area increase. So the challenge is to not break the low-power design—be aware of when level shifters need to be placed in, how isolation cells are handled, etc.

To do this, typically a tool takes in one of the power format files—either IEEE 1801 or CPF (for now, at least)—which describes the power intent. The tool then utilizes that information to determine where and when to put in a level shifter. That said, there are always different goals with different customers–sometimes it’s area, sometimes it’s timing –and the weighting of those can be different so there is flexibility within the toolset for the user to trade off things.

A second area where power and test intersect is in the DFT logic, which itself needs to be power aware. It shouldn’t consume much power or any power at all during the functional mode or mission mode, thereby minimizing the power consumption of the test logic itself.

Stephen Pateras, product marketing director for silicon test at Mentor Graphics, agreed that the test itself should not provide power issues. “In other words, when you’re applying the test you’re not increasing the power of the device or the ability of the device to deal with the power levels. You don’t want to increase your average power during test beyond what the design has been architected for. That’s a big issue because test generally tends to exercise a device in a much greater way than is done functionally.”

Pateras: Test should not add power issues.

Another area where power and test merge, and one of importance for users, is the amount of power consumed on the silicon device at test time.

“Even though low-power design has been a big buzz for a while and is in fact a reality, in the test engineers were hit with the power problems very early on. The main reason for that is if the goal of a manufacturing test program is not to just comprehensively test the chip but also to do it in a cost-effective manner, it means test as much of the chip as possible. That corresponds to a lot of activity on the chip, and activity means a lot of power draw potentially exceeding the power budget,” Ruiz said.

But just how accurate is this testing?

“It’s kind of ironic that your worst-case chip behavior in terms of power is actually during test because you artificially create random activities to exercise your test coverage, but at the same time you keep drawing current,” said Qi Wang, technical marketing group marketing director for Cadence solutions marketing. “This perspective means that you have to overdesign your power distribution network to accommodate for the worst case happening during test. However, in the real case it is overdesign, which kills performance and silicon area.”

Wang: Overdesign risks.

Interesting, he pointed out that the power management functionality already on the silicon can be leveraged to achieve low-power test. “However, this is the most challenging because you have to change your test methodology and enhance your flow. If you want to do this, you need a way to control the domain on/off and isolations by the tester, not by the circuit functionality,” Wang explained.

What users really need
Going forward, LSI’s Banerjee said yield is another aspect of test that could use some enhancement. Having a tighter loop between what the ATPG tool says and having it tied into the power estimation tools to actually see what happens on silicon would be really beneficial.

She said the technology LSI uses has been enhanced and is a lot more power-aware than it had been in the past and the company is definitely leveraging that. “It’s basically related to the activity of the patterns. Scan tends to exercise a lot more of the design than would normalized be exercised in typical mission mode. When that happens, we run the risk of having unnecessary fallout or yield loss because of that increased power consumption, so we could end up throwing away a defect-free part.”

“They’ve got switches in place to address the activity factor,” she continued. “Unfortunately that conflicts with pattern count because typically to reduce your pattern count, you want to run a lot more stuff in parallel but you want to reduce activity you want to run less in parallel. So they are kind of conflicting problems, but both need to be solved. So it would be nice if there was a way to be able to iterate and do some exploration between power savings and effectively test time in one go. That way you can get the power savings that you need but not shoot yourself in the foot when it comes to test time. I think they have the hooks in place to do that with all of their capabilities. It’s not something they can do and publish a generic recipe that would work for all designs but if they could provide a framework for the individual users to do that assessment or exploration, that would help.”

Power-aware testing of stacked devices
When it comes to implementing power-aware test on true 3D ICs, there may be additional complexities—or maybe not.

Synopsys’ Ruiz contends that test is actually the easiest issue for 3D IC. “What is a 3D IC stacked die? There’s already the ability to put in DFT to access chips, there’s technology to access multiple chips on a board—that’s called boundary scan IEEE 1149.1. Stacked chips tend to look like chips on a board and there are already existing test standards to do that. There’s already ability to put a boundary scan around the chip and there is ability to generate patterns. There’s ability to access, there’s a standard to describe dealing with multiple chips and there is ability to generate patterns, so all of the core and fundamental technologies are already available and customers are simply using them straightforward,” Ruiz concluded.

Ruiz: 3D test is a snap.

Mentor Graphics has similar thinking on this and detailed its strategy for 3D-IC design, verification and testing in March. And in June, Cadence and Imec said they developed an automated test solution for 3D ICs.