October 2011 - Semiconductor Engineering

More Knobs To Turn
By Ed Sperling - 28 Oct, 2011 - Comments: 0

Some of the hardest stuff is already done when it comes to saving power. Many engineers are quite well versed in managing multiple power islands and designing with sometimes dozens of voltage rails. There has even been massive progress in controlling gate leakage through a variety of materials and now 3D structures. There also is much more that can be done to improve energy efficiency, rangi... » read more

Experts At The Table: Improving Yield
By Ed Sperling - 27 Oct, 2011 - Comments: 0

y Ed Sperling Semiconductor Manufacturing & Design sat down to discuss yield issues with Sesh Ramaswami, senior director of strategy at Applied Materials; Luigi Capodieci, R&D fellow at GlobalFoundries; Kimon Michaels, vice president and DFM director at PDF Solutions; Mike Smayling, senior vice president at Tela Innovations; and Mark Mason, director of data integration at Texas Instrum... » read more

The top 20 ain’t what it used to be
By Chris Mack - 27 Oct, 2011 - Comments: 0

Looking back on data of the annual top 20 semiconductor companies since 1987, it’s amazing how much has changed. In my last post I looked at all the companies that went bankrupt, spun-out, or merged their way into or out of the top 20 list. Change is definitely a constant in this field. Now, let’s look at the makeup of the 2010 list of top semiconductor companies. Here is the list, as g... » read more

SOI Conference Shows SOI Driving Key Roadmaps
By Various Writers - 21 Oct, 2011 - Comments: 0

By Adele Hars The 2011 IEEE SOI Conference, held in Tempe, AZ last week was not one to miss…but I did. Happily, I got the papers right away, along with observations shared by some of the folks who did get there. Highlights include excellent and insightful papers from ST, ARM, IBM, Intel, Leti, Peregrine and GlobalFoundries, plus many more that indicate SOI-based technologies are at th... » read more

Experts At The Table: Mobile Design Challenges
By Ed Sperling - 21 Oct, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss the increasing challenges of designing for mobile devices with Qi Wang, technical marketing group director at Cadence; Cary Chin, director of technical marketing for low-power solutions at Synopsys; Bernard Murphy, CTO of Atrenta; and Dave Reed, senior director of marketing at SpringSoft. What follows are excerpts of that conversation. ... » read more

Early Software Development And The Supply Chain
By Achim Nohl - 20 Oct, 2011 - Comments: 0

By Achim Nohl In my last blogs I have been focusing on introducing the technical advantages of virtual prototypes in the context of debugging embedded software. In this blog I would like to introduce how this can impact an entire supply chain. The increasing complexity of software in terms of code-size, functions and layers, along with multicore SoCs, also demands more capable debug solutio... » read more

The Next SoCs
By Ed Sperling - 20 Oct, 2011 - Comments: 0

By Ed Sperling The number of changes that will hit the IC market over the next few years is almost staggering by any standard—past or present. In addition to the relentless pressure of Moore’s Law, there will be new materials, new structures, and new models for developing and packaging chips. System-Level Design asked executives from across the SoC ecosystem what will change, what’s d... » read more

Software Takes Control
By Ed Sperling - 20 Oct, 2011 - Comments: 0

By Pallab Chatterjee The idea that SoC and system design are a mix of hardware and software, in the form of both application software and firmware, has been in place for more than 60 years. But the emphasis is beginning to shift. The traditional approach has been to create the highest-performance circuit design, with some control options for flexibility, and then use this adaptable "platfor... » read more

Derivative Designs Demand Discipline
By Ed Sperling - 20 Oct, 2011 - Comments: 0

By Ann Steffora Mutschler By and large most designs today are derivatives, meaning they don’t start from a blank slate. And while that gives engineering teams a starting point, it also can make adding new IP blocks or changes to the design problematic, with the potential for increased routing and timing issues along with considerable pain to back-end engineers and delays in chip schedules. ... » read more

VIP: Behind The Velvet Rope
By Ed Sperling - 20 Oct, 2011 - Comments: 0

By Ann Steffora Mutschler Some years ago, as engineering teams began to incorporate more protocols into designs and as those protocols grew in sophistication and complexity in order to deliver additional performance, the verification task grew concurrently. At the same time, the design IP market was growing as complexity drove re-use of components, along with verification components—most com... » read more

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