Experts At The Table: Improving Yield

First of three parts: Risks of early adopters; tighter coupling of design and manufacturing; expected yields at 20nm and in stacked die; effects of double-patterning and variability; new rules and PDKs.


y Ed Sperling
Semiconductor Manufacturing & Design sat down to discuss yield issues with Sesh Ramaswami, senior director of strategy at Applied Materials; Luigi Capodieci, R&D fellow at GlobalFoundries; Kimon Michaels, vice president and DFM director at PDF Solutions; Mike Smayling, senior vice president at Tela Innovations; and Mark Mason, director of data integration at Texas Instruments. What follows are excerpts of that conversation.

SMD: As we move down the Moore’s Law curve, how will yield be affected?
Mason: Every time we move down a node we anticipate a certain level of entitlement, both in performance and in terms of cost per function. One of the things that plays into that is yield. It’s our expectation that yield, over time, will go to very high levels. The question is what will be the difficulty in ramping yield to the entitlement yield that you expect. We are dealing with that using design for manufacturability methodologies to ensure that we get to that level.
Smayling: As we move beyond 28nm we will see more factors that have a quantification kind of problem. When we began using thin gate oxides at atomic thicknesses we ran into problems. We ran into random dopant fluctuations because of discrete problems we didn’t expect. We will see those kinds of problems as we continue to shrink geometries.
Michaels: Final entitlement yields in established markets will be just fine. That’s always been the case. In fact, the time it has taken the industry to get to those points has been fairly consistent. But we’re going to see here is more train wrecks early on. Like the transition to copper we have more immature materials, more variation and new failure mechanisms. And we have a lot more parametric failure mechanisms that are going to cause a lot of challenges in distributions of initial yields, both in the fabs and in the foundries.
Capodieci: We’re in violent agreement here. One of the issues is that at 28nm and beyond, the physical design is going to have a very tight coupling with manufacturing. All of the methodologies that we have developed at 90nm, 65nm and 40nm now become essential. The early train wrecks could be avoided, but only through a tight collaboration between the manufacturer, the foundry, the IP providers and the designers, coupled with a methodology for verifying all of this. We’re talking about a DFM ecosystem that needs to play together. But whether this ecosystem is here and pervasive is another matter.
Ramaswami: If I can contain my comments to the through-silicon via and chip stacking, the challenge we see is that while part of the via is done by the foundries or the fabs, how well it’s done is determined by the back-end guys—that might be the foundry or the packaging house. It’s a guess, too. You don’t know how well you’ve done until everything is done. The second part has to do with all the stresses that you’ve built up on thin wafers, which are fully processed. We still don’t know, once the wafers are de-bonded, how they’re going to survive through to packaging.

SMD: How good is yield right now for 28nm?
Michaels: At 28nm there’s a lot of new materials and new integration, which inherently makes yield more challenging. The foundries are working to solve that, but the proof will be in mass production.
Mason: 28nm from a yield ramp at this point does not feel terribly different than the previous nodes I’ve worked on. There are challenges. We have a list. We are working them with our foundry partners. That’s what we do at every node. We expect to deliver entitlement yield ramps on 28nm on time and according to the plans we’ve set.
Capodieci: Yields look good. We’re on target for delivering on time. The key will be whether the physical design will comply with the new methodologies. Yield will be excellent for those designs we have implemented already. With the implementation of certain recommended rules I feel very confident that will work. But if you’re talking about designs that get shrunk from the previous node, those will have some churn. They will need to jump on new CAD methodologies and new verification. The question is whether the design and manufacturing are in sync.

SMD: As we look forward into the next node and into stacking of die, will it be the same yield ramp as for other nodes?
Capodieci: At 20nm, the ramp looks steeper because of the introduction of a possible set of disruptive techniques that right now are still up in the air. We don’t know which one we’re going to bring to high-volume manufacturing. That includes double patterning and a host of different techniques. That will depend on how ready the physical implementation will be. For critical layers, if you cannot decompose them your yield is going to be zero because you cannot tape out with any foundry. We’re already working to make those designs compliant.
Ramaswami: The challenge we see is how to minimize variation, whether it’s chamber-to-chamber or across the wafer. A lot of the work we are doing in process control and components, such as how the valves open and close, is all about chamber matching and wafer matching. A second area is lineage roughness. One or two nanometers can have an impact on performance.
Michaels: Once you look at stacking chips, and you’re only testing 3D chips, it’s very expensive to throw it out. What’s going to be required from the foundry perspective is controlling the variability as well as understanding whether the wafer is within spec. We can’t rely just on wafer probes at the wafer level anymore.
Mason: Yield is something you get when you multiply a lot of numbers less than one together. It’s a function of area. If you have a stacked system, but it has all this area in it, that impacts yield. It also has extra processes in it that impact yield. Nothing yields 100%. So once you multiply all these processes together, then by definition you’re going to have more challenges. We also have to carefully define what we’re talking about. As a customer you’re concerned about the yield package, but as process engineers we’re concerned about the yield of the logic circuits vs. the memory. That’s another layer of complexity.

SMD: We’re used to designing using a linear approach, but complexity will require all of this to be done concurrently between design and manufacturing. Who’s responsible for making sure that happens and will it work?
Smayling: The communication between design and manufacturing has always been a critical part of success. What we’ll need to do more is communicate unambiguously and in a less-burdensome way for both the manufacturing and the design side. There are efforts under way for open DFM and open PDK standards to make this communication more universal and clearer.
Michaels: The physical layer is becoming a place where you potentially differentiate in a negative way by causing problems. That requires tighter interaction between the design and the foundry. But the PDK in a design-rule manual, as a contract between the design team and the foundry, is a fallacy. It’s impossible to guarantee that even with guard-banding. Even if you address every potential corner case, problems exist. We saw that at 40nm. That’s what needs to change.
Capodieci: We have been working on this for many years. We need to enrich the design-rule manual and the PDK with additional constructs. We’re seeing some of those in the IP domain, but we also need constructs from the verification side. Pattern-based verification is working well today. We will see libraries of patterns to transfer information back and forth and share ownership across the physical design and with the foundry.
Ramaswami: Whether it’s lithography, patterning or packaging, we’re trying to figure out what are the design tools that are required. What are the process conditions required, no matter who we work with? In the 3D space we’re working closely with Synopsys with capacitance and stress modeling.
Mason: In TI we have 65 years of semiconductor manufacturing history in-house, but we also use foundries. We understand all about building wafers and we can communicate that to the foundries. But there is a danger in this concept of better communication and having the designers know all about this stuff. The design flow is already pretty busy just getting the design out, so you have to be pretty careful about burdening the design community with design information they’re not quite sure what to do with. You have to build systems that automatically inform the design flow without disrupting the design process. You can’t just push information up the design flow. That’s helpful for conversations but not for design.

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