April 2012 - Page 3 of 4 - Semiconductor Engineering

2.5D Leverages Existing Tools On The Way To 3D
By Ed Sperling - 05 Apr, 2012 - Comments: 0

By Ann Steffora Mutschler As design and manufacturing issues with true 3D design continue to be worked out, interim 2.5D technologies are moving ahead as engineering teams leverage this packaging-driven approach to manage heat, cost, area and yield. Technologies such as Wide I/O memory support 2.5D, and when combined with logic they allow engineering teams to realize a performance increase,... » read more

New Processes Define New Power Plans
By Ed Sperling - 05 Apr, 2012 - Comments: 0

By Pallab Chatterjee FinFETs, stacked die, heterogeneous interposers, TSVs, 450mm wafers, new interconnects and everything with MEMs and sensors is what the last few weeks have brought. A number of major announcements, technology releases, conference updates have identified these technologies as the future of IC design. At ISQED, Robert Geer, chief academic officer at the College of Nanosca... » read more

Reliability Concerns Grow
By Ed Sperling - 05 Apr, 2012 - Comments: 0

By Ed Sperling Knowing when to signoff on an IC design has always been as much art as science, matching engineering experience with managed risk. As ICs become more complex, however, even the most advanced chip companies are getting things wrong. Some of this can be fixed through software and some of it can be tweaked with programmable firmware. But some of it may have to be fixed in the ne... » read more

Power, Applications Drive New Thinking On System Planning
By Ed Sperling - 05 Apr, 2012 - Comments: 0

By Ann Steffora Mutschler Throwing out the term ‘application-driven power-aware design methodology’ may sound like gobbledygook to some, but this concept is keeping many technologists awake at night—especially considering video games that heat iPads to 100+ degrees centigrade (near melting). The problem is very real, and potentially painful in more ways than one. The iPad example, al... » read more

Getting Ready For Stacked Die
By Ed Sperling - 05 Apr, 2012 - Comments: 0

By Ed Sperling The move toward stacking of die has always been a series of disconnected pieces and vague promises for the future, but in the past few months the scenario has changed radically—and so has the commentary. All three of the Big Three EDA vendors now have at least some of the pieces in place for 2.5D stacking and are working on a full 3D flow. Two of the biggest FPGA vendors, A... » read more

Experts At The Table: Designing At 28nm And Beyond
By Ed Sperling - 05 Apr, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to talk about design at future process nodes with Naveed Sherwani, president and CEO of Open-Silicon; Charles Janac, chairman and CEO of Arteris; Frank Schirrmeister, group director of product marketing for Cadence’s System Development Suite; Behrooz Zahiri, vice president of marketing at Magma (and currently director of marketing at Synopsys), and... » read more

Reliability Verification For Smart ICs
By Arvind Vel - 05 Apr, 2012 - Comments: 0

By Arvind Shanmugavel The electronic brains behind today’s advanced systems are smart ICs, paving the way for consumer electronics, energy, biomedical, automotive and avionics industries. Power efficiency and system integration are keys to the success of these smart systems. The IC industry has swiftly responded with state-of-the-art low-power techniques and chip integration initiatives f... » read more

PathFinder Solution For Full-Chip IC ESD Integrity
By Various Writers - 05 Apr, 2012 - Comments: 0

This paper describes how PathFinder helps designers meet ESD guidelines and identify “weak” areas of the design (layout or circuit) most vulnerable to ESD failures. It also demonstrates how PathFinder can be used for early prototyping and design exploration, especially when clamp cells are inserted inside the core region of the chip. To download this white paper, click here. » read more

FinFET Vs. Tri-Gate
By Barry Pangrle - 05 Apr, 2012 - Comments: 0

By Barry Pangrle A large portion of the Common Platform Technology Forum, recently held in Santa Clara, was dedicated to presentations about 14nm process technologies and FinFETS. If you missed the event and are interested, many of the presentations are available from a link off of the Common Platform home page. Dick James wrote a nice article about GlobalFoundries’ claim that its FinFETS ar... » read more

Crunch Time
By Ed Sperling - 05 Apr, 2012 - Comments: 0

Never have so many things conspired to make design so difficult—at least not at the same time. At the center of this cornucopia of challenges is power, because more functions and more things now have to fit into a power budget that remains fixed. While some components in a complex SoC may run at lower voltages, you can be assured that others will run hotter and at higher voltages—at leas... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy