Crunch Time

The confluence of power, process and physics will permanently alter IC design.


Never have so many things conspired to make design so difficult—at least not at the same time.

At the center of this cornucopia of challenges is power, because more functions and more things now have to fit into a power budget that remains fixed. While some components in a complex SoC may run at lower voltages, you can be assured that others will run hotter and at higher voltages—at least during peak demand for a logic subsystem or a processor core. And the spikes that result still have to be taken into consideration and modeled effectively enough so they don’t burn a hole in the chip or otherwise render it inoperable.

So what’s different? Power is no longer just a factor in design. It has become a starting point that is every bit as important as function. The two are intertwined like some Gordian knot. And whatever is considered the maximum voltage is probably already too high at advanced nodes and inside of stacked die. More area has reduced the opportunity to solve some problems with guard-banding because the overhead is unacceptable, both from a cost and performance standpoint.

There are some exotic solutions being considered. Microfluidics pulsing liquid through a chip really can cool it effectively. But designing this kind of mechanical microchannel architecture where liquid is propelled through tiny chambers isn’t isn’t in the budget for most chips–and possibly not any chips. And, of course, it’s not very convenient to carry around a container of liquid nitrogen with your portable device.

The more realistic solutions will come in two places. One is from the design side, where stacking and Wide I/O have the ability to dramatically reduce the amount of power needed to drive signals by reducing the distances and widening the channels. The EDA industry is just beginning to take this approach very seriously.

A second solution will come on the manufacturing side in a couple of areas. One is new structures—FinFETs, carbon-nanotube FETs, tunneling FETs—which control leakage much more effectively than planar FETs. It remains uncertain whether EUV will ever become commercially viable or whether self-assembly—using a template that allows finFETs to literally set up automatically on a substrate—will replace it. The second part of this comes from new materials, such as fully depleted silicon on insulator and new gate oxides and insulating strategies, such as air gap, which can better control leakage.

But in all cases power will remain one of the key components of design, from the initial architecture stage to final manufacturing signoff and test, and touching everything in between from ESL models to RTL and verification.