July 2012 - Page 5 of 5 - Semiconductor Engineering

Power Mode And State

By Luke Lang - 12 Jul, 2012 - Comments: 0

By Luke Lang Low-power designs that use power shutoff (PSO) and multiple-supply voltage (MSV) will have circuits that operate at various voltages, including no voltage. To describe the combination of allowable voltages in a design, CPF uses power mode, and UPF 1.0 uses power state. In CPF, each power mode represents one combination of the states of all power domains. In UPF 1.0, each power ... » read more

Dealing With Variability

By Barry Pangrle - 12 Jul, 2012 - Comments: 0

By Barry Pangrle Process, voltage and temperature, a.k.a. PVT, are well known to designers who are working to complete “signoff” for their designs. In order for a design to be production-ready, it’s necessary to ensure that the design is going to yield parts at a sufficiently high percentage for profitability and that it will still operate within the expected variation of the process and... » read more

Opportunity Lost

By Ed Sperling - 12 Jul, 2012 - Comments: 0

The more software that gets written by hardware companies, the more they understand just how large the gulf has grown between the hardware and software mindsets. In part this is a cultural issue. Software and hardware engineers have different tools, different goals and different mindsets. But to an even bigger extent, it’s a legacy issue. And unlike hardware, legacy in software can begin a... » read more

Executive Briefing: The Next Five Years

By Ed Sperling - 12 Jul, 2012 - Comments: 0

Low-Power/High-Performance Engineering talks with Synopsys CEO Aart de Geus about what's changing in design, the role of hardware and software, and what comes next. [youtube vid=RxDGmKRBbPQ] » read more

Getting Paid For Efficiency

By Ed Sperling - 12 Jul, 2012 - Comments: 0

Over the past couple of years the electronics industry has woken up to the fact that saving energy and prolonging battery life is a very good thing. It can be marketed, used as a differentiator, and companies can charge a premium for battery-saving technology. In high-end devices, the incremental cost of adding even additional processors tends to get buried. In extremely price-sensitive mar... » read more

Experts At The Table: Pain Points

By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation. LPHP: Where will the pain points be going forward? Kariat: 20nm is... » read more

Bubble Gum and Scotch Tape

By Ann Mutschler - 12 Jul, 2012 - Comments: 0

It’s always extremely interesting to talk with actual design engineers, trudging through the trenches of challenges like 3D design. Recently, I was able to speak with Robert Patti, chief technology officer, vice president of design engineering and a director at Tezzaron Semiconductor. The company has been putting 3D designs together for quite some time so I expected to hear that they are u... » read more

Disaggregation And Re-aggregation

By Ed Sperling - 02 Jul, 2012 - Comments: 0

The proliferation of platforms, subsystems and IP of any sort, as well as the move to stack die in 2.5D configurations, will force a realignment of the ecosystem. For the moment, it appears that vertically integrated companies such as Apple and Samsung have a distinct advantage. It remains to be seen just how substantial that advantage really is, however. As chips become a collection of more... » read more

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