Experts At The Table: Pain Points

First of three parts: Economic impact of double patterning, local interconnects and varability; physical effects in stacked die; increasing complexity; yield issues; who will move beyond 20nm.


By Ed Sperling
Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation.

LPHP: Where will the pain points be going forward?
Kariat: 20nm is a big pain point already for technology, but it’s also a pain point for economic reasons. It looks like 14nm won’t be much more, and we don’t have any idea about 7nm. At 20nm, there are two sets of challenges. We’re introducing lots of new technologies that change the design flow. There is double patterning and local interconnects. The device variability will be significantly higher. Layout-dependent effects are going to be more of a problem. They’ve been a problem at 28nm, and they’ll be more of an issue at 20nm. We’re seeing a big different between the people who will build large SoCs and those who won’t. Each has a very different set of issues. There is a thinning going on here as companies drop into analog and specialized power.
Kulkarni: The pain points I’m seeing are from connecting the dots between chip, package and system. That involves power, signal, noise, EM, EMI, on-chip ESD. Driving all of that will be 3D IC. That’s what we’re losing sleep over.
Murphy: The big challenge we see is increasing complexity, and the need for physical awareness to be part of the architecture. If you look at what it takes to get gates down on silicon, you have to have a lot of configurable IP. That includes bus fabrics, the CPUs themselves, the cache memories. You think of this kind of stuff typically as an algorithm and performance problem, but it’s becoming a physical problem, as well. You can’t separate those anymore. You have to find ways to get physical insight—power, performance and area—while you’re developing the architecture. And that’s becoming more acute as the designs become bigger.
Buch: The biggest problem is going to be yield. The question at 20nm isn’t whether we’re moving to double patterning. It’s at what level do big designs yield. People who are going to 20nm are doing big GPUs and other chips. But getting those designs to yield at a good enough rate will be the big problem. We’ll get to 20nm; 14nm, who knows? How are we going to make the economics work? If you look at the design costs and the number of people and the design time and then you look at the yield, at what numbers does it all add up? People are dropping off on how fast they go to the next node. At 20nm there will be more drop-offs. Can TSMC keep up with Intel and Samsung? This will decide what kinds of designs get done. That is the biggest unknown at this point.
Moll: We’re seeing 28nm is already painful, for the usual reasons. The back end is really a front-end problem now. You have to figure out what you’re going to do on the back end when you’re architecting your chip—where your pads are, where your subsystems are, how you’re going to move things around, what it’s going to look like and how you’re going to connect things. What we’re seeing is instead of a rush to system on chip, it’s a rush to system in a corner of a chip. In a corner of a chip you can put a subsystem that is very substantial. There are caches and CPUs. What we see is a hierarchical approach being generalized to chip design. It used to be one person as the top-level architect. There is still a person in the middle, but that’s more of an integration person. And there are subsystems with entire teams developing large pieces. One thing that’s clear is you can’t do one of these chips all by yourself anymore. Maybe if you have something that’s very regular you can, but if you’re doing a mobility SoC with a huge catalog of IP, it’s impossible. The people who win will be the ones who apply their resources in a more intelligent fashion. They will figure out what differentiates them and shop for the rest.

LPHP: Is the solution just working with partners better, or is it rethinking chips entirely?
Vinod: The economics dictate we will see a few big companies reaching 14nm. We’ve been talking about SoCs for a long time. They’ve been systems, but they haven’t been put together like systems. Other pieces have to feed into it. That’s one of the dynamics changing there. We talk about IP a lot, but in reality there’s a long way before it’s put into practice.
Moll: In mobility, there’s a big land rush now. Everybody wants to have a mobility product. There are multiple companies getting into that market. At the same time, because it’s very competitive, the windows are getting shorter. Companies that used to do these chips in 24 months are now doing them in 18 months, and the ones doing it in 18 months are now doing it in 12. This is a double whammy. Not only are the chips more complicated, but they’re trying to shrink the development time as much as possible. This is where the hierarchical assembly process needs to be really well oiled.
Murphy: We all have gotten used to ARM being the CPU of choice, but Imagination has shown there is a market for star IP beyond just the core CPU. That’s a very popular GPU. It’s complex. It’s creating new challenges from an integration point of view. It’s a big hunk of logic, and you have to fit that big hunk of logic into something else. You can’t just say the floor plan is wide open. You have to carve out space for it. There may be an opportunity for other big subsystems like this. If you look at the market around servers, this is very hot. Oracle, AMD and Samsung are working on very small footprint servers that are multicore with a lot of bus fabric. Those could be subsystems themselves.
Kulkarni: All these things are about power, not just wireless applications. We see a spectrum of applications. If you have a disk controller running at 15 watts, they want to reduce it to 12 watts. We have customers at 65 watts to 70 watts in the server farm area, and they want to reduce it to 60 watts. What we find is everyone is facing power because power is noise and associated issues. It applies to IP within the context of the SoC around it, and multiple IPs, as well. How do you integrate that from power point of view? And with 3D ICs, each IC may have different thermal issues. There are more issues coming into the picture. There are a lot of issues with the package and the interposer and through-silicon vias. You cannot look at a single chip or even an SoC anymore. It’s multiple domains that impact each other.
Buch: And how are people going to make money out of all of this? TSMC has all these different processes for high performance, low power, and now there’s going to be just one at 20nm. With EDA tools, we’ve spent years trying to outperform everyone else, but the reality is Synopsys or Cadence tools can implement it. You need a platform these days. You’ll have an interconnect, and maybe an ARM core, and then how do you program all of this? Software is going to drive differentiation. That doesn’t mean problems don’t have to be solved. But I don’t seen anyone rising above the vendor or the IP noise and be able to say they’ve got something way better than everyone else. To solve this, someone will have to come up with a software idea, which is going to be the differentiator.

LPHP: How many tools from a company such as Altera are internally developed versus externally developed? And are the internally developed ones running out of steam?
Buch: I came over from Magma. Now I’m in charge of the tools, so I have a unique perspective. What you really need to do is bring in outside tools and have a bake-off and see which one is better for your needs. There are certain designs where tool ‘A’ is better than tool ‘B,’ but there are very few of those and you usually can get the job done either way. There are designs out there where you need to use hierarchy and break up the design, but the tools will get there. The question is how you make money as a tools vendor. Magma was seeing the number of customers going down, and if you don’t have a full portfolio you get squeezed. That commoditization is happening across the board everywhere.
Kariat: There is too much work to be done and it’s hard to make money because there are too few people who want to do the design. There are five people doing an SoC. But there are a lot more people in the other market who are doing a lot of IP design. Bosch is doing automotive chips. But they’re not in this domain at all. They’re at 2 microns. To go to 20nm and 14nm and serve a handful of companies that won’t use many of our tools, it’s a challenge.
Murphy: In the early days, IDMs developed their own CAD organizations. If this trend continues, they will have to develop their CAD organizations again. There are only a few companies that will need it.

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