March 2013 - Page 4 of 6 - Semiconductor Engineering

Nanoscale Wiring
By Kathryn Ta - 21 Mar, 2013 - Comments: 0

By Kathryn Ta The TEM image (below) taken at Applied Materials’ Maydan Technology Center shows a series of 20nm-wide trenches in cross section. These tiny structures – about 1/5000th of the diameter of an average human hair – are similar to the interconnects used to wire the billions of transistors in next-generation microchips. You can see that each trench is partially filled with coppe... » read more

Computational Lithography
By Various Writers - 21 Mar, 2013 - Comments: 0

Computational lithography has become an integral part of design since the 130 nm process node. New techniques continue to be developed to extend the steady node shrink year after year. To read this white paper, click here. » read more

Next-Generation Signoff Analysis
By Various Writers - 21 Mar, 2013 - Comments: 0

The electronic design industry continues to push the limits of moore's law through smaller and smaller process nodes. As we reach 45nm, manufacturing and process control becomes increasingly difficult, making it imperative that manufacturability issues be addressed much earlier in the design cycle to avoid costly respins and chip failures. Physical and electrical effects at this node challen... » read more

Breakthroughs Required
By Ed Sperling - 21 Mar, 2013 - Comments: 0

Linear progressions have a hypnotic effect on even the smartest people. They lull everyone into thinking that progress—or at least a progression—is a straight line, with little or no recognition that things are changing around the edges. The periphery is definitely changing, though. And over the next couple of process nodes, the semiconductor manufacturing industry either will have to fi... » read more

More Photons Are Good
By Michael Watts - 20 Mar, 2013 - Comments: 0

By Michael P.C. Watts Scatterometry is the favored approach to monitor complex 3D nano-structures in production. At SPIE Advanced Lithography, KLA introduced a new generation of their scatterometry metrology system. The new system expands the number of different measurements; know internally as multi-multi-multi. Scatterometry relies on measuring the diffraction patterns from a test diffr... » read more

Directed Self Assembly, double patterning and crying in beer
By Michael Watts - 20 Mar, 2013 - Comments: 1

In the creative, or desperate, rush to find ways to pattern 10 nm node using double patterning immersion 193nm lithography, a designer from ARM is left “crying in his beer” at the consequent design difficulties. This heart rending admission was one of many insights that came at the sessions on Directed Self Assembly (DSA) at Advanced Lithography. Double Patterning has become the -we have... » read more

What’s In A Name?
By Subi Kengeri - 20 Mar, 2013 - Comments: 0

By Subi Kengeri Consumers continue to demand smaller, faster and more energy-efficient electronic devices, driving the semiconductor industry to accelerate development of commercially viable chips on more advanced nodes. However, these new nodes don’t just appear by magic. It takes a great deal of careful planning to develop and deliver a process technology platform that offers competitivene... » read more

Over 50% Of Smart Phones And Tablets Leverage SOI
By Various Writers - 18 Mar, 2013 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ In a recent press release, the SOI wafer leader Soitec said that chips built on its SOI wafers were found in over half of the smartphones and tablets in the market worldwide. 50%? That’s a lot! How do they figure that? The answer: RF. [caption id="attachment_809" align="alignleft" width="549" caption="As seen here... » read more

A Balancing Act
By Ann Mutschler - 14 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler If you stay current on data center trends, you are well-versed on the fact that Intel reported last June energy proportionality has effectively doubled server efficiency and workload scaling beyond what Moore’s Law predicted. What does this have to do with power management of SoCs? Cary Chin, director of marketing for low-power solutions at Synopsys, said tha... » read more

Sprint To The Finish Line
By Ed Sperling - 14 Mar, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss future challenges, pain points, and how the supply chain is being reconfigured with Chi-Ping Hsu, senior vice president for R&D in the Silicon Realization Group at Cadence. What follows are excerpts of that conversation. LPHP: How important is it to be at the front end of Moore’s Law? Hsu: Strategically, it’... » read more

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