Breakthroughs Required

The cost of manufacturing chips isn’t going down as quickly, if at all, at each new node. Now what?


Linear progressions have a hypnotic effect on even the smartest people. They lull everyone into thinking that progress—or at least a progression—is a straight line, with little or no recognition that things are changing around the edges.

The periphery is definitely changing, though. And over the next couple of process nodes, the semiconductor manufacturing industry either will have to figure out a strategy for reducing the cost of manufacturing semiconductors, or it will have to start working in a different direction altogether.

There are several factors at work here:

1. Lithography. This is by far the best-known and understood roadblock to progress. After billions of dollars of investment and years of delays, EUV still isn’t ready. For anyone familiar with this technology, that’s not particularly surprising. This is hard stuff to get right. The big problem is the power supply, but there are scattering and sidewall issues that are so difficult to solve they make your brain hurt. It may never be fully solvable, which is why so much attention has turned to directed self-assembly in recent months. DSA has its own pitfalls, though, and it remains to be seen whether it can ever truly replace 193nm immersion.

2. Metrology. So far there is no viable replacement for CD-SEM, which is to metrology what 193nm immersion is to lithography. Beyond 20nm, it’s harder to get a clear image to take accurate measurements. What comes next is a matter of debate, because while solutions do exist they also are destructive to the features they’re measuring. In a world defined increasingly by the low double digits of the nanometric scale, this is a big problem.

3. Design and DFM. The cost of designing complex systems on chip is going up significantly, which is part of the reason companies such as STMicroelectronics and Broadcom are making the most of the 28nm node. There are no finFETs yet, no double patterning, and there is the option now used by ST of fully depleted silicon on insulator with body biasing. Moving forward requires a big jump in complexity, time, and much more restrictive design rules, and even then yield is something no one is talking about yet. And with chipmakers now responsible for the wafer instead of just known good die, that’s a big leap of faith required. Add in 450mm wafers and the risk and cost may go significantly higher without any guaranteed returns.

One alternative, which will likely unfold in several steps, is through innovative packaging. In some respects, this is a sharp left turn from the feature shrinking, but ultimately it could be complementary. The big hurdle in 2.5D stacking has been the cost of the interposer, but given the rising cost of designing, manufacturing and characterizing chips at advanced nodes, this may pale in comparison. Full 3D stacking still has some issues to work out, notably around the TSVs.

What also will likely unfold, once stacking becomes more mainstream, is an ecosystem of IP—probably fully integrated subsystems and platforms developed as full die produced at whatever process node makes the most sense. For memory and logic, this is likely to be at leading-edge nodes. For analog and mixed signal IP, it likely will be at older nodes. And for I/O IP, it likely will vary depending upon whether it is a new standard or legacy.

Progress is hardly at a standstill, no matter what happens. If EUV miraculously appears on the horizon with a power supply, the path forward may indeed be linear for another couple of process nodes. But even then, there are challenges.

What’s encouraging, though, is that progress won’t stop no matter what happens. It will be less linear, but you don’t always take a straight path to reach a better solution.

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