March 2013 - Page 3 of 6 - Semiconductor Engineering


Experts At The Table: The Trouble With Low-Power Verification


By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power verification with Leah Clark, associate technical director at Broadcom; Erich Marschner, product marketing manager at Mentor Graphics; Cary Chin, director of marketing for low-power solutions at Synopsys; and Venki Venkatesh, senior director of engineering at Atrenta. What follows are excerpts of that conversat... » read more

Wanted: New Metrology Funding Models


By Mark LaPedus The shift toward the 20nm node and beyond will require new and major breakthroughs in chip manufacturing. Most of the attention centers around lithography, gate stacks, interconnects, strain engineering and design-for-manufacturing (DFM). Lost in the conversation are two other critical but overlooked pieces in the manufacturing puzzle—wafer inspection and metrology. ... » read more

Reaching For The Reset Button In Lithography


By Mark LaPedus Amid ongoing delays and setbacks, extreme ultraviolet (EUV) lithography and multi-beam e-beam have both missed the 10nm logic node. So for the present, chipmakers must take the brute force route at 10nm by using 193nm immersion with multiple patterning. Now, it’s time to hit the reset button. For the 7nm node, chipmakers currently are lining up the lithographic competition... » read more

Making An Impression with Nanoimprint


By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss the trends in lithography with Mark Melliar-Smith, president and chief executive of Molecular Imprints Inc. (MII), a supplier of nanoimprint lithography tools. SMD: How do you view the IC industry now? Melliar-Smith: It’s truly incredible work that this industry continues to do. The industry will see its way f... » read more

Directed Self-Assembly Grows Up


By Mark LaPedus At last year’s SPIE Advanced Lithography conference, Christopher Bencher, a member of the technical staff at Applied Materials, said the buzz surrounding directed self-assembly (DSA) technology resembled the fervor generated at the famous Woodstock rock concert in 1969. This was clearly evident from the tumultuous and free-flowing movement that threatened the status quo o... » read more

Verifying Your Intent


Design rule checking (DRC), layout versus schematic (LVS) and electrical rule checking (ERC) are physical verification techniques that are mandatory today to check a design and its structures before manufacturing. Checking electrical characteristics of a design is one thing. Verifying power intent is quite another. And the overlap of the two is an intriguing concept. Case in point: Checking fo... » read more

Swimming In Data


By Ed Sperling So many warnings about data overload have been issued over the past decade that people generally have stopped paying attention to them. The numbers are so astronomical that increases tend to lose meaning. Nowhere is this more evident than in the semiconductor metrology world, where files are measured in gigabytes. And at each new process node, as the number of transistors a... » read more

Programming The Future


By Joanne Itow After Achronix and Altera made significant announcements involving FPGA products and Intel’s advanced manufacturing technology, I decided to take a closer look at some of the market numbers involved. Just to recap, in February, Achronix announced the company began shipping the first FPGA device manufactured on Intel’s 22nm, Tri-Gate process technology. One week later, Altera... » read more

Chasing Rabbits


“Now, here, you see, it takes all the running you can do, to keep in the same place. If you want to get somewhere else, you must run at least twice as fast as that!” —Lewis Carroll, Through the Looking Glass By David Abercrombie As I discussed in my previous article, the use of stitching can greatly reduce the number of double patterning (DP) decomposition violations that a designer ... » read more

The Learning Imperative


By Tom Morrow An often under-appreciated component of Moore’s Law has been the massive learning and education effort required to sustain continuous improvement at the incredible rate predicted by Gordon Moore nearly 50 years ago. The industry regularly calculates the contribution of lithography-based scaling, wafer size increases, and yield improvements necessary to keep pace with aggressive... » read more

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