Verifying Your Intent

New areas of reliability checking are being developed to include transistor-level power intent analysis.


Design rule checking (DRC), layout versus schematic (LVS) and electrical rule checking (ERC) are physical verification techniques that are mandatory today to check a design and its structures before manufacturing. Checking electrical characteristics of a design is one thing. Verifying power intent is quite another. And the overlap of the two is an intriguing concept.

Case in point: Checking for ESD (electrostatic discharge) is part of ERC. “Whenever we talk about and ESD reliability verification it has to be verified from an electrical standpoint,” said Arvind Shanmugavel, director of applications engineering at Apache Design. “We’re not trying to verify any intent as such. ERC is a platform where you can actually write several different queries on your actual netlist to understand if your ESD protection devices are correctly connected or not so again this is completely to do with the physical design side. It’s not anything to do with the actual intent of power from an RTL perspective.”

Typically, as they move toward tapeout, designers start putting in ESD clamp devices or ESD diodes.

“Those diodes need to be present in certain power domains, in all the different I/O pads and also in between power domains,” Shanmugavel noted, adding there are two parts of checking the electrical rules—whether a diode or an ESD protection device is present or not, and how effective the diode or clamp element is going to be.

KT Moore, group director of product marketing for the silicon signoff business unit at Cadence said there are a lot of different ways to check reliability. “In general when you do design and layout there is always a set of rules that you check—minimum spacing, minimum width, etc.—and normal DRC will check that. When you get into these multi-voltage domain kind of designs you might want to start making sure that things are not only DRC correct, but DRC correct within the context of the voltage domain that you are in. Let’s say in a multi-voltage or multi-VT design, you have high-voltage devices and weak voltage devices and you want to make sure that the right voltage is connected to the right device and you don’t necessarily want to spend a whole lot of time during that. A good way to do that is with an ERC.”

However, Shanmugavel doesn’t see any relationship between the power intent file and ERC, either now or in the future. “When you are designing a low-power processor or an application processor, during the architecture specification you will say that you have certain blocks in one voltage domain and different blocks in another voltage domain to reduce the power. And then certain blocks are going to be shut off during the sleep mode while other blocks are going to be running full steam during the sleep mode. You can specify that in the architecture phase and also in the RTL, but how do you know you can actually verify it when you implement it? From an architectural specification point you have all these power domains running at different voltages, you have different sleep modes, you have different transitions from one mode to another, but verifying that on the physical side is actually extremely difficult.

He compared it to RTL verification. “With RTL verification you typically write some kind of a testbench to verify if the input provided and the output provided match up. On power intent verification it’s a little more complicated. For example when you turn on a block you have to isolate all the inputs coming into the block through isolation devices. Let’s say you are having signals go from Block A, which is power domain A, to two Block B, which is power domain B, you need to have level shifters but typically there is no single way of verifying all of this. That is how UPF and CPF were actually invented because of the need to be able to verify all these different low-power techniques.”

There is no single answer for solving these problems, and vendors have taken divergent paths in trying to find solutions. Matthew Hogan, product marketing manager at Mentor Graphics, contends that traditional approaches don’t go far enough.  New methods to address power intent verification are available to stretch the boundaries of the traditional understanding of reliability checking and ERC to include transistor-level power intent analysis. He explained that while Mentor’s ERC technology initially focused a lot on ESD, as more was learned about the problem space and the company looked beyond backend verification of DRC/LVS, they realized the technology could be leveraged in the area of reliability verification.

“This allowed us to go after things like multiple power domains in designs and circuits, where we put together SoCs and IPs from usually very disparate places, while making sure that we don’t fall over any electrical overstress type issues or other things like that,” Hogan said. “A lot of times, people will try and do detailed SPICE simulations or try and do some sort of analysis and it’s often the case where unless you can hit the circuit with just the right input vectors for your simulation and you’re experienced enough to understand the subtle variations that might occur in the output waveform to indicate a problem. Some of these more subtle reliability-type issues are very difficult to identify, much like DFM went after how to improve yield or improve the design side of things.”

However, reliability doesn’t deal with the hard and fast that LVS does. “From a DRC perspective, it means we can’t manufacture it correctly. From an LVS perspective, it doesn’t match what you think your source netlist looks like. A lot of these reliability-type issues manifest themselves in more subtler ways and it’s really from an improvement of the design from a holistic perspective that people want to go after now because they’ve got the base groundwork of the traditional DRC/LVS/ERC-type checking,” he said.

Physical verification tools check for design consistency: Are you consistent with the design rules from a DRC perspective? LVS checks consistency based on what you said you wanted versus what you implemented. But how do you check the design against your design intent?

“We’re able to detect those design conditions and really go forward, again on this whole reliability idea of saying, ‘What you have is what’s correct in the LVS, but it doesn’t represent your design intent.’ These are the types of issues that you’re going to see manifest when you start using this design in the real world. It becomes very prevalent where you are doing these SoCs with IP reuses because you might not own all of the IP that’s inside there. You might buy that block or reuse that block from another project, so there might be some subtle design interactions that you, as the user of this piece of IP, might not be aware of because you didn’t design and develop it from the ground up,” Hogan pointed out.

Mentor’s technology also supports the UPF format. “[This] allows you to overlay—not so much in a dynamic simulation perspective, because obviously that’s the nirvana that everybody talks about—but it really is this multi-state static analysis. You can take different snapshots of your design and how your power intent overlays on top of your physical implantation and determine if the correct design cells are in place, if the correct transistors are in place for the retention cells for the level shifters and all of those things, to be able to cope with the power intent that you’ve told the design about through this UPF file that basically carries along and morphs throughout the design process.”

Further, the transistors that are implemented as part of these structures must be considered. For example, the transistor that makes up a simple inverter – you must make sure it’s got its bulk tied to the correct voltage through the contacts, and then it must be verified. “When you take it up that extra level into the HDL space where a lot of people are doing this verification, you still don’t know if you implemented the transistors underneath correctly. Do I have this rectangle for a double or a triple well drawn in the right spot? Are there transistors that are outside of that region that are going to cause me a problem?  It becomes particularly important when I have a little design ECO or respin that I need to do – maybe you verified the block standalone but now there are some extra transistors that are included in the mix. Did they also have the correct ties and how does that work as a whole ecosystem?  It just takes one transistor to be in the wrong spot in the wrong power domain and it can shut off a third of your chip or something ridiculous like that,” he added.

At the end of the day, power is one of the most challenging things to quantify, because it depends on what you are doing, Cadence’s Moore pointed out. “It’s not just one thing that gets you. When you look at reliability, that’s where power really comes into play. The more power you draw, the more current you are drawing, and the more wear and tear on the device you are going to have. But leakage is a different animal. It’s not so much wear and tear as it the effect that it has. You care more about leakage when you have wireless or handheld devices because that’s always drawing current on your battery. Design teams care about both of those things and it’s hard to find one thing that’s going to give all the answers.”

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