April 2013 - Page 5 of 6 - Semiconductor Engineering

RTL Restructuring
By Various Writers - 11 Apr, 2013 - Comments: 0

We all know that hierarchy created for logic design must often be adjusted to map to a physical implementation. Logic hierarchy is typically constrained by non-implementation factors, especially organization of teams working on different components and use of legacy or 3rd party IP. Physical hierarchy, on the other hand, must partition the logic to fit detailed implementation tool capacity limi... » read more

Power? It’s The Apps, Stupid!
By Shabtay Matalon - 11 Apr, 2013 - Comments: 0

Shabtay Matalon When I bought my first iPhone, I envisioned using it mostly to make phone calls and occasionally to view e-mails and browse the Web. For navigation, I used a separate GPS. But all this changed when I realized that I can use the Waze App on my iPhone for real-time navigation or to play games while listening to music on a boring coast-to-coast domestic flight. These new “apps�... » read more

Optimizing Cost-Performance-Schedule With A Chip-Package-System (CPS) Methodology
By Various Writers - 11 Apr, 2013 - Comments: 0

To meet smart device requirements with high levels of sophistication from an exceedingly small device running off a battery, the underlying electronics must evolve at a rapid pace. To read more, click here. » read more

The Power Of Logic
By Barry Pangrle - 11 Apr, 2013 - Comments: 1

By Barry Pangrle CMOS logic has been dominant since nMOS gave way back in the 1980s. Dynamic logic, like domino, has seen its application in high-speed and often hand-crafted datapath circuits. The potential energy efficiency of operating at near-threshold voltage is very enticing but having to deal with variability issues has made engineers reluctant to try to do more at lower voltages. The q... » read more

Improved Efficiency
By Bhanu Kapoor - 11 Apr, 2013 - Comments: 0

By Bhanu Kapoor We constantly hear about process technology advances and their impact on power consumption of ICs, but the power management techniques have remained the same over last few process technology generations. Power gating, dynamic voltage and frequency scaling, and threshold voltage scaling have been the key power management techniques since the 90nm process technology. Clock gating... » read more

Uncertainty Ahead
By Ed Sperling - 11 Apr, 2013 - Comments: 0

If finFETs work as planned, it’s likely they will show up in every complex SoC for decades to come. Adding another dimension to transistors has enormous potential at advanced nodes, and maybe even at older nodes. 3D transistors also could be part of stacked die, and they can be combined with fully depleted SOI—two other options for reducing power. Moreover, it’s likely that whatever G... » read more

Experts At The Table: FinFET Questions And Issues
By Ed Sperling - 11 Apr, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the current state and future promise of finFETs, and the myriad challenges, with Ruggero Castagnetti, an LSI fellow; Barry Pangrle, senior power methodology engineer at Nvidia; Steve Carlson, group director of marketing at Cadence; and Mary Ann White, director of product marketing at Synopsys. What follows are excerpts ... » read more

A Low-Power Riddle
By Synopsys - 11 Apr, 2013 - Comments: 0

By Cary Chin I’m thinking of a mobile electronic device, introduced in 2012, at the high end of its market segment, eventually to be named “Product of the Year” for 2012. But it wasn’t introduced without the usual flurry of energy-efficiency related problems, with initial complaints such as, “the product worked well, but the battery drained way too fast, even when it was turned off!�... » read more

Solar Reality Check
By Michael Watts - 11 Apr, 2013 - Comments: 0

By Michael P.C. Watts There are plenty of papers at conferences talking about new patterning, materials and process approaches to solar cells. While listening, I wondered if there was any realistic chance for a new technology. The solar cell business is exponentially growing but has become rather gruesome over the last year or so…is there any real opportunity to insert new technologies ? ... » read more

Challenges In IC And Electronic Systems Verification
By Aveek Sarkar - 11 Apr, 2013 - Comments: 0

By Aveek Sarkar Designing successful electronic systems that can meet the needs of a challenging and quickly evolving mobile market requires design teams to solve critical problems such as power efficiency, unrealistic schedules, and cost-down considerations. In this first of a three-part series, we will look at these challenges. Part 1: The Growing Challenges Designing electronic systems ... » read more

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