Experts At The Table: FinFET Questions And Issues

First of three parts: Less leakage, but uncertainty about reliability, and big challenges with power density and moving designs from one foundry to the next; pin accessibility becomes more difficult; fixed widths; thermal unknowns.


By Ed Sperling
Low-Power/High-Performance Engineering sat down to discuss the current state and future promise of finFETs, and the myriad challenges, with Ruggero Castagnetti, an LSI fellow; Barry Pangrle, senior power methodology engineer at Nvidia; Steve Carlson, group director of marketing at Cadence; and Mary Ann White, director of product marketing at Synopsys. What follows are excerpts of that conversation.

LPHP: What are the pros and cons of dealing with finFETs?
Pangrle: On the pro side, rather than just controlling the channel on one side you can gate it on multiple sides. The hope and promise is that you get better control over the channel, better performance, and less variability. There are other challenges in terms of device manufacturing. As you keep making the line widths finer and finer, it raises challenges regardless of whether it’s finFETs or planar.
White: The whole promise of better power overall, whether it’s dynamic or leakage, is because the pinched off channels have better electrical characteristics overall. Shorter-height cells, from a standard-cell perspective, will probably be better. Memories are definitely using this effectively. And overall you get better density, even with wider transistors. The con part is that this is an emerging technology. We don’t have a lot of details about it. We don’t have a lot of details about reliability, which is important with this much density in such a small area.
Carlson: When you look at the progression of 28 to 20nm, with 20nm not everyone saw the same value proposition as with 28. Everyone is rushing ahead hoping that with finFETs the 20nm metal stack will be the solution. It takes everything we’ve learned from 20nm and the middle- to back-end of line and just plugs in the new transistors. They’ll be better because of the higher drive and lower leakage. But if you look at the divergence of the transistor design and the way they’re being made and the tradeoffs they’re making, if you talk to the IP and the analog developers, the transistor characteristics are so different across the different foundries that it’s a complete redesign. They’re not taking the same schematics from one foundry and dropping it in and tweaking for another. The reason people are going forward is to get scaling back on track. We’re rushing ahead and hoping the gate capacitance and reliability and some of these other factors don’t stall us again.
Castagnetti: The promise is for better transistor characteristics. In terms of better gate control, there is definitely an advantage in exploiting the sub-threshold slope behavior and being able to operate devices at a lower voltage for a power benefit. The challenge that I continue to see is that process technology does not scale nearly as close as it would need to in order to maintain a power-efficient envelope. At the end of the day, you have twice as many transistors in the same area and the power density doubles. That’s going to be a challenge.

LPHP: Do finFETs offer a way to deal with that increased density by lowering leakage and presumably reducing electromigration?
Castagnetti: Leakage has improved, but the dynamic power is still there. Gate capacitance is likely to be higher because of the 3D structure. And how do you handle that? With all the focus over the last 10 years to handle leakage, we may have forgotten how to handle dynamic power. Some of the design styles will have to be reconsidered.
Pangrle: We may have to go back to some of the optimization we did 10 years ago.
White: We see a couple things to help on that. The operating voltage is lower. It looks as if the nominal voltage will probably settle at 0.8 instead of 0.9 volts. So if you just do the V squared, at 0.8 that’s about 25% dynamic savings just by lowering the voltage. A second thing that can help is the smaller cell height. A 10-track can be equivalent to a 12-track height. It’s denser, but you compensate by lower operating voltages with smaller area.
Castagnetti: If we can connect to them, yes.
White: It’s all promise, but there have been some early numbers. (Intel senior fellow) Mark Bohr showed 37% savings on dynamic current.
Castagnetti: We need to differentiate between a 22nm node versus 14nm or 16nm nodes, which are really 20nm.
White: Yes, the big secret is that 14nm and 16nm are actually 20nm gate-drawn lengths.
Castagnetti: On the one hand you can get away with a smaller gate pitch footprint. But if you still have 20nm metals, you may not be able to connect with them as easily as you like.
White: That’s true. With shorter cell height, the pin accessibility does get harder.
Carlson: And then couple that with double-patterning challenges.
Pangrle: An interesting side of this is when you put it all together. If you’re just looking at the device performance gains, you still have to hook them all together. When Intel came out with 22nm parts compared with their 32nm parts, for ones running roughly at the same frequency, it looks as if they got about a 19% reduction overall. That’s good, but it’s not 37% to 50%.
White: The drop in voltage will be the biggest benefit.
Pangrle: If you can reduce the leakage, that gives you the opportunity to lower the threshold voltage. That’s been the barrier up to this point. To control leakage we had to keep Vth high, which means you have to keep VDD higher.

LPHP: How much harder is it to design a finFET compared with a planar transistor?
Castagnetti: With digital logic, it’s not much more difficult. But if you look at the analog design starts—and every design today is not just logic—the question is how to deal with the quantification of width. That’s the new thing with finFETs. The widths come in fixed numbers and multiples of that.
White: Both the width and the number of fins.
Castagnetti: The concept that it is either this width or that width and nothing in between needs to be comprehended.
Carlson: It’s not so much the design of the transistor itself. It’s the interaction between the transistors that’s more difficult. Some of it is just geometries. With smaller geometries you get layout-dependent effects, well-proximity effects and stress. And then you add the third dimension to that and all the parasitics that come along with that. The current running to there is not uniform, so you end up having to put in a mesh model to get a more accurate conclusion about what the current densities are going to look like. And you have these higher-performance transistors and metal interconnects that are designed for a different generation, so all of a sudden there are reliability concerns about which we don’t have enough data to say whether this is really an issue. You can’t just fatten up the metal line, either. You have to move stuff around it, so it’s pretty intrusive to do something because of the reliability concerns.

LPHP: How much of reliability is based upon double patterning?
Carlson: EUV will eliminate the double patterning part.
Pangrle: One of the big questions with finFETs is reliability. Thermal issues certainly will come into play with finFETs—maybe more than with planar transistors.

LPHP: Now you have to get heat out of deeper channels between transistors, right?
Pangrle: Yes, because the transistor is now sitting on edge—and this is assuming you’re using bulk. You have a very narrow conduction path to get heat out. Some would argue that’s not the best way to begin with. Another issue is that variability of these devices is temperature-related, too. We don’t know how this will play out. A bad scenario is that this becomes an issue and designers have to go back and do some kind of guard-banding. At that point we start losing the advantages of a new technology.
Carlson: Or you start moving to an SOI process. There is about a 100x difference in the thermal connectivity with an SOI process, but the economics aren’t there yet.
Castagnetti: I don’t expect the thermal aspects to be different from what the SOI guys deal with today. We’ll have to see what it does to finFETs. In my mind the bigger challenge is how these fins and stress patterns are going to behave in the context of package and putting the package on a board or a system. Are we going to see some instant variability coming back so that we need to look at this up front to understand it better?
White: The temperature variation will be significant. We know they’ll behave a lot differently hot versus cold—125 degrees and minus-40 degrees might not be the right parameters anymore.
Pangrle: People are looking at power gating. Are companies looking at moving away from more header switches and looking at more footers?
White: We definitely are seeing more footers being used. In terms of finFETs, it’s too early to actually say. We haven’t done commercial libraries. We have done it only for customers that are proprietary. The big foundries have not released stable PDKs or process you can build libraries on. You’ll probably see things like burn-in happen again. You’ll have to package the part and run them through different temperatures. We used to do that with military parts, where we ran them through different temperatures to simulate 30-year life averages.

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