July 2013 - Page 5 of 10 - Semiconductor Engineering

A Tale Of Two Standards
By Ed Sperling - 18 Jul, 2013 - Comments: 0

By Ed Sperling It could well be one of the strangest developments in standards history. Two competing standards for power formats were rolled out in the middle of the last decade and aside from a few cries of foul they fell below the radar screen of most chip designers and architects for a half-dozen years. Fast forward to the present and the Common Power Format (CPF) and Unified Power Form... » read more

Changes And Challenges
By Ed Sperling - 18 Jul, 2013 - Comments: 0

At 130nm, the shift to copper interconnects and 300mm wafer sizes was considered to be the most difficult transition in its long and incredibly efficient history. The next chapter will be even tougher. It’s not that change is a foreign concept to semiconductor design and manufacturing. In fact, it’s probably the only constant over the past 50 years. But in the past, those changes tended ... » read more

The New Hybrid World: Vision And Reality
By Brian Fuller - 18 Jul, 2013 - Comments: 0

SAN FRANCISCO—You know the famous scene from the movie “The Graduate,” in which a young Dustin Hoffman is offered investment advice by a businessman. “I want to say just one word to you…just one word. Are you listening? Plastics.” Today, Hoffman’s character Benjamin Braddock might hear two words: “Integrated objects.” At least that’s how Ross Bringans from PARC sees... » read more

Experts At The Table: 450mm Fab And Facilities Challenges
By Mark LaPedus - 18 Jul, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future 450mm fab and facilities challenges with Gerald Goff, director of the project management office for fab design and construction at GlobalFoundries; Joe Cestari, president of Total Facility Solutions; Ivo Raaijmakers, chief technology officer of ASM International; and Michael Brain, senior director of the Fab S... » read more

Foundries Eye 300mm Analog Fabs
By Mark LaPedus - 18 Jul, 2013 - Comments: 0

By Mark LaPedus In 2009, Texas Instruments changed the semiconductor landscape when it opened the industry’s first 300mm fab for analog chips. Until then, analog chip production was conducted in fabs at 200mm wafer sizes and below. With a 300mm fab, TI potentially could gain a die-size and cost advantage over its analog rivals. On paper, a 300mm wafer provides 2.5 times more chips than a... » read more

High NA EUV Litho May Require Larger Photomask Size
By Jeff Chappell - 18 Jul, 2013 - Comments: 0

By Jeff Chappell With extreme ultraviolet lithography (EUV) potentially being used in pilot production in a few years, it raises the question of larger photomasks sizes—will the industry need them, and if so, when? While there has been discussion of late about the possible need to transition to a larger mask size, veterans of the mask business may feel it's déjà vu all over again. Back... » read more

450mm: Out Of Sync
By Mark LaPedus - 18 Jul, 2013 - Comments: 0

By Mark LaPedus The IC industry has been talking about it for ages, but vendors are finally coming to terms with a monumental shift in the business. The vast changes involve a pending and critical juncture, where the 450mm wafer size transition, new device architectures and other technologies will likely converge at or near the same time. In one possible scenario, 450mm fabs are projected ... » read more

MEMS Foundries Play Waiting Game
By Mark LaPedus - 18 Jul, 2013 - Comments: 0

By Mark LaPedus For years, the foundries in the microelectromechanical systems (MEMS) business have been patiently waiting for the MEMS integrated device manufacturers (IDMs) to outsource some or all of their production. The MEMS foundries are still waiting for that development. Because MEMS are custom devices tuned to a proprietary process and toolset, IDMs still prefer to use their own f... » read more

You Can’t Get There From Here
By David Abercrombie - 17 Jul, 2013 - Comments: 0

By David Abercrombie In my last article, I reviewed the aspects of cell design that are affected by double patterning (DP). This time, I’ll discuss how automatic routing is affected by DP. Let’s begin by looking at the interaction between decisions made at the cell design level and decisions made at the routing level. One key routing decision is whether or not you will allow cell-to-cel... » read more

Mobility Gets A Boost With Expanded Epi Applications
By Applied Materials Writers - 17 Jul, 2013 - Comments: 0

By Jeremy Zelenko Even as industry moves into the era of the high k metal gate (HKMG) and FinFET transistor, chipmakers continue to seek ways to improve device performance. One of the latest advances and the subject of an Applied Materials announcement made today is to extend epitaxial deposition from PMOS to NMOS transistors. Implementing an NMOS epitaxy (epi) process in addition to the estab... » read more

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