450mm: Out Of Sync

Extremely high costs, complexity in the rollout schedule and uncertainty on the customer side add lots of question marks to the move to bigger wafer sizes.


By Mark LaPedus
The IC industry has been talking about it for ages, but vendors are finally coming to terms with a monumental shift in the business. The vast changes involve a pending and critical juncture, where the 450mm wafer size transition, new device architectures and other technologies will likely converge at or near the same time.

In one possible scenario, 450mm fabs are projected to move into mass production at the 7nm node in 2018, meaning the next wafer size transition could occur in concert with a significant change in materials. At 7nm, chipmakers hope to move from today’s finFETs to those with III-V materials as a means to boost chip mobility.

The so-called high-mobility finFETs may use bulk or fully depleted silicon-on-insulator (FD-SOI) technology. By then, the industry hopes that extreme ultraviolet (EUV) lithography is ready. However, there are signs that 450mm fabs initially will use 193nm immersion scanners, not EUV.

The vast changes represent a mixed bag for equipment makers. On one hand, the new challenges enable vendors to innovate and develop new tools. On the other hand, there is some troubling uncertainty. For some time, the equipment industry has stressed the importance for chipmakers to synchronize on a precise 450mm fab timeline to help toolmakers gain a reasonable and timely return-on-investment.

To date, however, chipmakers appear to be moving at different speeds, and their respective timelines for 450mm are still cloudy. Intel wants to be first in 450mm. TSMC and GlobalFoundries don’t want to be first or last. And Samsung apparently has changed its aggressive stance in the 450mm race. “Samsung is now like a bride with cold feet at the wedding,” said Dean Freeman, an analyst with Gartner.

It’s too early to say that 450mm will suffer from the same troubling “start-and-stop” phases that plagued the 300mm wafer transition in the 1990s. And it’s also unclear if the industry is ready, and can afford, to juggle all of the new and expensive technologies at once.

“There are quite a few complex transitions that are occurring in the next five years,” said Kirk Hasserjian, corporate vice president for the Silicon Systems Group at Applied Materials. “We’re seeing an explosion of new materials being used. The patterning roadmap is getting more complex. On top of that, we are doing the 450mm transition. That has actually brought up a question. Can you actually do a wafer size transition when you have all of these different scaling transitions we have to do?”

To make it a successful transition, the industry must synchronize its 450mm efforts on a precise roadmap, Hasserjian said. In addition, the industry must still address the 450mm R&D funding model. “There is a lot of work that can be done throughout the supply chain to make sure this will be a successful transition,” he added.

Deep pockets
The transition also will require another key component. “It will require big bucks,” said Ajit Manocha, chief executive of GlobalFoundries. “Only a few companies can really afford these expensive fabs.”

At 14nm/22nm, IC design costs are $150 million on average, process development costs are $1.3 billion and a 300mm fab is $7 billion, Manocha said. In comparison, a 450mm fab is expected to cost $10 billion to $15 billion, according to some estimates.

One company cannot afford to go it alone. So chipmakers lean heavily on various R&D organizations for help. In fact, the R&D organizations—CEA-Leti, Imec, G450C and Sematech—also provide a window into where the chipmakers are heading and in what time frame. In contrast, GlobalFoundries, Intel, Samsung and TSMC have talked about their future plans, but most have kept their detailed roadmaps close to the vest.

One R&D entity, the Global 450 Consortium (G450C), is focusing on 450mm tool readiness, baseline process development, and test wafer availability. “In 2016, our goal is to have a roadmap to high-volume manufacturing,” said Paul Farrar, general manager of the G450C.

Meanwhile, Imec has a 300mm cleanroom, which includes a small 450mm extension. Last year, the Flemish government set plans to invest in a new 450mm cleanroom at Imec, which, in turn, will convert the facility into a 450mm R&D pilot line. It will break ground on the new facility in early 2014, said Ludo Deferm, executive vice president of business development at Imec.

For its part, Imec is focusing on process development in the 450mm R&D pilot line. The cleanroom will be completed by the end of 2015. Then, Imec will install the 450mm fab tools, with plans to have a full process flow by 2016.

Imec’s decision to implement 450mm at a certain node depends on the demands of its R&D partners. In CMOS, Imec’s R&D partners are GlobalFoundries, Intel, Micron, Panasonic, Samsung, TSMC, SK Hynix, Fujitsu and Sony. “We control our own schedule,” Deferm said. “The new cleanroom will be ready for 2015. Then, we can move in the 450mm equipment for a full processing flow at 7nm or 5nm, or whatever is requested by the IDMs at that moment.”

By then, the industry will make a major materials change. “The introduction of high-k materials at 45nm and 32nm was a major change,” said Luc Van den hove, chief executive of Imec. “At the 7nm node, we will see the first-generation of high-mobility materials. Introducing these mobility materials will be of the same complexity as high-k.”

Today’s finFETs will likely scale to 10nm. Then, at 7nm and 5nm, the industry hopes to migrate to finFETs with III-V materials in the channels. Currently, there are five leading candidates for so-called high-mobility finFETs—finFETs with germanium (Ge) for the PFET; finFETs with Ge for both PFET and NFET; and finFETs with Ge for PFET and III-V materials for NFET. Meanwhile, the two possible spoilers are tunnel field-effect transistors (TFETs) and nanowire-based gate-all-around finFETs.

The roadmaps
The industry hopes to roll out these technologies in several phases. Based on the current roadmaps from Intel and other chipmakers, the first 450mm pilot lines would appear in 2015 and 2016. Initially, the pilot lines may process wafers at the 10nm node, based on today’s silicon-based finFETs. At 10nm, Ge and III-V materials may not be ready for prime time.

“Usually, what you do is take your qualified node from 300mm and implement that on 450mm, because you need a reference,” said An Steegen, senior vice president of process technology at Imec. “Then, you would take your reference node from 300mm, which is 10nm. Likely, that’s still silicon finFET based. It’s difficult to predict, but it’s likely that germanium and III-V will be too soon for the 10nm node.”

The first high-mobility finFETs are expected to appear at 7nm, with the emergence of a finFET with Ge in the PFET and tensile silicon in the NFET. Ge has nearly four times the electron mobility compared to silicon.

Presently, Imec and others are in R&D with Ge and III-V materials for finFETs on 300mm wafers. At 7nm, the industry will transfer the Ge-based finFET work from 300mm to 450mm fabs. So in effect, Ge finFETs are expected to become the first products to ramp in high-volume 450mm fabs, she said. That could occur in 2017 or 2018.

Then, the industry will move to a next-generation high-mobility finFET at 7nm or 5nm. The leading candidate is Ge for PFET and indium gallium arsenide (InGaAs) for NFET. “The way we are inserting those materials is with epitaxial growth. So you take a silicon substrate and you grow epi in your trenches and you get your FETs,” Steegen said. “There are other ways in implementing those devices, where you have big blankets of epi wafers in germanium and III-V. And you etch your fins and build your finFETs that way. If you do it that way, you have big blanket wafers, which are no longer silicon. It’s a route we are verifying, which has challenges just like the other technique.”

The big question is cost and the throughput of the epi process. “If you go with the (epitaxial growth) scheme, that’s wafer based. Your throughput is the same with 300mm and 450mm,” she said. “Where you are going to see differences is in the loading effects. The bigger the wafer sizes, the more variations you might see on your wafer.”

Not surprisingly, however, the FD-SOI camp has a different view. “Some products can afford to go to finFETs,” said Paul Boudre, chief operating officer at Soitec. “We think it’s much more difficult to manufacture finFETs on bulk. We need to move from bulk to something else.”

In its latest roadmap, STMicroelectronics is currently ramping up a 28nm FD-SOI process based on a planar structure. The plan is to extend planar FD-SOI to the 14nm and 10nm nodes, which are expected to debut in 2014/2015 and 2016/2017, respectively.

The process design kits for 14nm FD-SOI technology will ship next quarter. In effect, the technology competes against the 14nm-class bulk finFETs. “From a foundry perspective, FD-SOI is a cheaper technology that offers the same performance,” said Maud Vinet, FD-SOI manager for CEA-Leti and the IBM Alliance.

Longer term, the SOI camp is looking at various SOI-based finFET options, including separate fin-on-SOI and fin-on-oxide (Fox) technologies. Like FD-SOI planar, the fin-on-SOI technology makes use of an isolation layer between the substrate and transistor. In contrast, Fox makes use of a bulk wafer. The doping isolation layer is removed, but the technology makes use of an oxide replacement fill. Fox promises to extend down to the 5nm node.

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