September 2013 - Page 5 of 9 - Semiconductor Engineering

Front End Comes To The Back End
By Jeff Chappell - 19 Sep, 2013 - Comments: 0

By Jeff Chappell For outsourced assembly and test (OSAT) houses either planning for or already offering through-silicon via (TSV) capability for their 3D packaging efforts, this has meant the front end is coming to the back end, in a manner of speaking. A bit of an exaggeration perhaps, as most generalizations are. But thanks to TSVs, in a very real sense some of what would typically be the... » read more

You Ain’t Seen Nothing Yet
By David Abercrombie - 19 Sep, 2013 - Comments: 1

I’ve been talking about double patterning for a long time now in this series of blogs. I thought it might be good to start looking ahead at what is next for multi-patterning (Don’t Panic!). As you may have been hearing or reading, it doesn’t look like EUV lithography is going to be ready for 10nm, and may not even make it for 7nm. This means that alternative methods of extending the exist... » read more

Blog Review: Sept. 18
By Ed Sperling - 18 Sep, 2013 - Comments: 0

By Ed Sperling It’s amazing how irresistible an engineer suddenly becomes when he has an FPGA prototyping board in his hands. Check out the photo of Synopsys’ Mick Posner in Taiwan. Cadence’s Brian Fuller digs into semiconductor startups, why there’s been such a lull, and how new startups are changing. Mentor’s John Day picks out a new product category from TI—inductance to... » read more

System Bits: Sept. 17
By Ann Mutschler - 17 Sep, 2013 - Comments: 0

Multicore memory management According to MIT researchers, it may be time to let software rather than hardware manage high-speed on-chip memory caches. Traditionally, managing the caches has required fairly simple algorithms that can be hard-wired into the chips but as multiple cores in SoCs proliferate, cache management becomes much more difficult. As such, MIT’s Department of Electric... » read more

Power/Performance Bits: Sept. 17
By Ann Mutschler - 17 Sep, 2013 - Comments: 0

Harvesting energy from light In a finding they believe could improve technologies for generating electricity from solar energy and lead to more efficient optoelectronic devices used in communications, researchers from the University of Pennsylvania and Duke University have demonstrated a new mechanism for extracting energy from light. They said the process is much more efficient than conven... » read more

The Week In Review: Sept. 16
By Mark LaPedus - 16 Sep, 2013 - Comments: 0

By Mark LaPedus In June, Crucial.com teamed up with Lou Ferrigno to invite all frustrated computer users to submit a short video showing their most fearsome, frustration-filled and computer-induced roar. Each video was evaluated according to a variety of factors, including volume, enthusiasm, perceived distress, frustration, anxiety, irritation and overall hopelessness. The memory module suppl... » read more

The Week In Review: Sept. 13
By Ed Sperling - 13 Sep, 2013 - Comments: 0

By Ed Sperling Cadence unveiled its next-generation emulation platform, greatly boosting the speed by up to 60x for embedded OS verification and by up to 10x for hardware/software verification. Overall, Cadence says the platform doubles verification productivity with a capacity of up to 2.3 billion gates. Cadence also reported that its mixed-signal LP flow allowed Silicon Labs to cut its MCU p... » read more

Experts At The Table: Process Technology Challenges
By Mark LaPedus - 13 Sep, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future transistor, process and manufacturing challenges with Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries; Carlos Mazure, chief technical officer at Soitec; Raj Jammy, senior vice president and general manager of the Semiconductor Group at Intermolecular; and Girish Dixit, v... » read more

Experts At The Table: Next-Generation IP Landscape
By Ann Mutschler - 13 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss predictions about the next generation design IP landscape with Robert Aitken, R&D fellow at ARM; Laurent Moll, chief technical officer at Arteris; Susan Peterson, group director, product marketing for verification IP & memory models in the system & software realization group at Cadence; and John Koeter, vice preside... » read more

Embedded Memory Impact On Power Grids
By Marko Chew - 12 Sep, 2013 - Comments: 0

Introduction Due to the overwhelming technical advantages of having on-chip memories, embedded memories are ubiquitous in most chip designs, and can comprise significant portions of a chip (upwards of 50%, according to some authors). Accordingly, a chip’s power grid design and analysis must account for the impact of these embedded memories, but design teams often struggle to resolve power... » read more

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