Experts At The Table: Process Technology Challenges

Last of three parts: After CMOS and futuristic technologies; the impact of 450mm wafers; variability and 3D structures; improving the economics of R&D; 4G LTE and 5G.

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By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss future transistor, process and manufacturing challenges with Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries; Carlos Mazure, chief technical officer at Soitec; Raj Jammy, senior vice president and general manager of the Semiconductor Group at Intermolecular; and Girish Dixit, vice president of the customer integration center at Lam Research. What follows are excerpts of that conversation.

SMD: If silicon runs out of gas in the distant future, the industry will require a so-called post-CMOS technology. Atomic switches, carbon nanotubes, graphene devices and spintronics are among the potential contenders. Any thoughts about these or other futuristic technologies?
Kengeri: All of these technologies are in the lab. It’s a matter of picking the right one. But it isn’t an easy decision. There are so many decision criteria. At the minimum, there are about 10 criteria. All of them need to be checked out. In some cases, we can assess them through estimates and simulations. There are some that must run on silicon. That means you need a pilot line to build the device. I personally believe that nobody in this industry has a clear answer yet. We do have a path finding funnel. We know the likely candidates, but we have not made a decision yet.
Jammy: I am not completely sure if we have a clear demarcation between a CMOS era and a post-CMOS era. For example, you have finFETs and FD-SOI. People would say these technologies were not classical CMOS even five years back. All of these futuristic technologies are interesting if you look at them from an applications perspective. As we move forward, there is a divergence of options and applications. Some specific applications may need carbon nanotubes. Then, it’s a question of integration for that application. But then, you ask if there’s enough volume and is there a justification in the market from a PPC criteria?
Mazure: It’s going to be application-driven. Graphene is actually not new to the industry. Graphene has been used as an electrode for the trench capacitor at Qimonda. It has been in manufacturing. Many of the so-called new materials are not complete unknowns. Graphene is actually a fairly good interconnect. But who knows how or when these things will appear. In this regard, the semiconductor industry has a track record of incremental changes.

SMD: Let’s shift to the wafer size transition. Any thoughts on 450mm?
Dixit: The industry learned a lot when we scaled from 200mm to 300mm. All of that learning is helping to scale 300mm to 450mm. It puts a different perspective in terms of product development. At this point in time, it’s assumed you will be starting with finFETs, primarily silicon-based finFETs, at 450mm. Then, it will quickly transition to whatever material is next. But there’s still a question when 450mm will happen. And granted, the economics are up in the air. We will be ready for 450mm. We have a lot of activity going on that front.
Mazure: I remember scaling up from 200mm to 300mm. That was a big issue. We will face some engineering issues with 450mm. The industry will be ready for 450mm when the time comes. From our side, we are already doing our homework to make sure that we know what’s required in terms of reliability. SOI manufacturing involves cleans, furnaces, metrology and other tools. All of these tools have to be available for making CMOS devices at 450mm.
Kengeri: If you zoom into one critical aspect, you have the economics. But the variability is a critical piece. We are talking about the variability of the wafer. We struggled to get and control the variability of planar. We’ve reasonably perfected that. Now, going to 3D has its own variability. 450mm is all of the things we learned from 200mm and 300mm. Plus, there is additional and significant variability. That can change the dynamics in terms of how you design the SoC. So, we will have to bring the SoC design into the fabrication, equipment and R&D ecosystem. This ecosystem is very complex. It’s getting even more complex. The interdependency is a lot more involved than ever.
Jammy: As we go towards these new technologies, and also 450mm, we have to start thinking about making chips from a completely different perspective. Addressing variability will require us to think about new solutions. For example, junction doping requires non-damaging, and very low junction-depth type of technologies, which don’t necessarily exist today. But we have to think about doing this on maybe germanium fins, III-V fins and silicon fins. So, you need a technique that is not in existence today. It has to be conformal and non-damaging. We’ve got to come up with new methodologies for that. At the same time, dopant fluctuation has to be controlled. The requirements out there are not completely addressed by existing techniques.

SMD: What happens to scaling if EUV is not ready?
Kengeri: That’s why the industry has multiple approaches. We can find a solution. It’s not impossible, but it’s a matter of getting there. If it’s not EUV, 3D TSV is a possibility. It could also move towards fully integrated monolithic SoCs, which is the preferred approach.
Mazure: Regarding the industry driver, it’s not going to be just the smallest feature size. We will move into new materials and substrates, which will need to be in place when the industry requires them.

SMD: What about the so-called “More than Moore” arena?
Mazure: We have been talking about scaling and reducing feature sizes. That’s true for digital. But if we look around, we are in a completely different era, where the systems—such as smart devices and wireless devices—are moving towards hybrid or heterogeneous integration. The value is the sum of different technologies, such as power management, connectivity, RF technologies, memory and digital signal processing. On the RF side of the semiconductor industry, there is already a very tight matching of device architectures and substrates. As we move forward, even in digital, we are going to see a tight coupling of the choice of materials and the architectures of the devices.

SMD: The industry is working on 450mm, EUV, stacked die and new device architectures. Who will do the R&D? And who will pay for it?
Jammy: This problem is something that has been around for a long time. The question is more fundamental. How do we reduce the cost of doing R&D? How do we improve the speed of R&D? That’s really what we at Intermolecular are trying to address. The other issue is where are the profits? In the industry, who economically benefits the most? And who is being asked to pay for the technology? The profit center is changing. Perhaps there is more money being made by the systems houses today than ever before. Once upon a time, the fabs could get a healthy margin. But maybe that’s changing rapidly, because of the costs and complexity involved. The suppliers are getting squeezed.
Kengeri: We’ve talked about the challenges. We will solve them as a combined industry. But R&D investment is becoming a bigger and bigger challenge. That’s that dollar part of it. There is also significant pressure to get a return. Time to market and time to volume are very critical. That’s why we tap into every R&D resource that’s possible in an efficient way. We at GlobalFoundries count on R&D from our global ecosystem. There are a few aspects to that. One, of course, is investment and where is it going to come from? Even if we had all of the money in the world, there are still going to be technical showstoppers. Second, we need the right talent. We also need the cycle times. Intermolecular, for example, has a solution to reduce the cycle times by being able to do some of the path finding in a more efficient way. So, in general, we tap into every possible source of R&D, whether it’s Imec, the IBM joint development alliance, or other partners. If you look at the IBM JDA, we have GlobalFoundries, IBM and Samsung. That’s where a lot of R&D is really done. They make the critical decisions. Once those decisions are made, we move it from the lab to the fab.
Mazure: As we go further to the next node, and then to the next node, research and development is becoming more and more concurrent. We’re basically confronted with more challenges, more materials and more choices. And in addition to that, we can no longer look at technology development and address it in a classical way. We have to take a more holistic approach, looking at design techniques and looking at the applications. This can only be done in a pre-competitive way. That’s why we have big R&D centers like Imec and Leti. There is also Sematech. There is another one in Japan called LEAP, which is looking at extremely low power design techniques, coupled with design architectures, libraries and materials.
Dixit: If you look at it from the equipment side and the overall industry, I don’t think R&D spending has gone down. The R&D has been on an increasing path all along. The question is how does the industry tap into pre-competitive R&D?

SMD: What keeps you up at night or what do you see as the biggest challenge? Is it 450mm, EUV, 3D, stack die or something else?
Kengeri: It’s not any one of them. What really keeps me, and our R&D teams, awake is how do we really provide a value for the customer node after node and time after time? Otherwise, the industry will not grow. Today, as a foundry, we’ve been able to provide a value so far. What about the next level? This is not just GlobalFoundries, but this includes the industry as a whole. It’s a big challenge. It’s like Moore’s Law. It’s been a self-fulfilling law for so long. Moore’s Law is one way to address scaling. But today, it’s not just that. It’s scaling on multiple levels and multiple dimensions. It all comes down to PPC value node after node. There are also economic realities. For example, who’s going to fund the R&D? At the end of day, we need to have a real silicon solution with the PPC metrics.
Dixit: There are major challenges, but we will find solutions. But I would prefer not to think of this as keeping me awake at night. I would like to characterize it like this–the industry is looking very exciting right now.
Mazure: What keeps me awake is the fact that we are in front of a very big tsunami. This big tsunami is something people call the third wave of wireless communications. The 4G LTE Advance or 5G standard is coming. This will enable more machine-to-machine communications. Machine-to-machine communications will add an incredible amount of new applications, which will translate into a lot of data transmission between your mobile devices and servers. This is the cloud. You will require more performance on your mobile device, but at a lower power consumption. This will require a number of new technologies.
Jammy: All of these technologies keep me awake. Not because I see them as huge problems, but I see them as great opportunities. One way to look at it is to fast forward 5 or 10 years from now. I don’t believe GlobalFoudries or any other foundry would say: ‘Here’s a 5nm generation technology.’ We will see more of a 5nm platform technology, where you’ve taken a customer’s design and added some memory, RF components and something else. That perhaps becomes a package. GlobalFoundries and other foundries have talked about it. That’s the direction we are heading.