External Resistance Reduction By Nanosecond Laser Anneal In Si/SiGe CMOS Technology


Authors: 1Oleg Gluschenkov, 1Heng Wu, 1Kevin Brew, 2Chengyu Niu, 1Lan Yu, 1Yasir Sulehria, 1Samuel Choi, 22Curtis Durfee, 1James Demarest, 1Adra Carr, 3Shaoyin Chen, 3Jim Willis, 3Thirumal Thanigaivelan, 1Fee-li Lie, 2Walter Kleemeier, and 1Dechao Guo 1IBM Research, 257 Fuller Road, Albany, NY 12203, USA, email: [email protected] 2GLOBALFOUNDRIES Inc., Albany, NY, USA, 3ULTRATECH, a division ... » read more

Trading Off Power And Performance Earlier In Designs


Optimizing performance, power and reliability in consumer electronics is an engineering feat that involves a series of tradeoffs based on gathering as much data about the use cases in which a design will operate. Approaches vary widely by market, by domain expertise, and by the established methodologies and perspective of the design teams. As a result, one team may opt for a leading-edge des... » read more

Effects of a Random Process Variation on the Transfer Characteristics of a Fundamental Photonic Integrated Circuit Component


Silicon photonics is rapidly emerging as a promising technology to enable higher bandwidth, lower energy, and lower latency communication and information processing, and other applications. In silicon photonics, existing CMOS manufacturing infrastructure and techniques are leveraged. However, a key challenge for silicon photonics is the lack of mature models that take into account known CMOS pr... » read more

Zeno Semi Expands On-Chip Memory


San Jose, Calif.-based startup Zeno Semiconductor is testing modifications and a smaller process node for the single-transistor 28nm SRAM chip it introduced in 2016, which could boost space for on-chip CPU memory by more than 2.5X, according to the co-founder and CEO of the company, Yuniarto Widjaja. The Zeno-1 transistor is built on standard CMOS processes, has a bi-stable bipolar transisto... » read more

Parametric Analysis, Design Guidelines for mm-Wave nm CMOS Transmission Lines


This paper focuses on nm CMOS transmission line design as distributed passive elements and their application in mm-wave integrated circuits. A variety of transmission lines such as coplanar waveguides (CPWs), shielded coplanar waveguides (SCPWs), and CPW with ground are analyzed in terms of their geometry and electrical properties. The parametric analysis of the various line types is based on a... » read more

AI Architectures Must Change


Using existing architectures for solving machine learning and artificial intelligence problems is becoming impractical. The total energy consumed by AI is rising significantly, and CPUs and GPUs increasingly are looking like the wrong tools for the job. Several roundtables have concluded the best opportunity for significant change happens when there is no legacy IP. Most designs have evolved... » read more

Leti’s Next Focus


Emmanuel Sabonnadière, chief executive of Leti, sat down with Semiconductor Engineering to discuss R&D trends, a new deal with Soitec, and the latest developments at the France-based research organization. Leti is a research institute of CEA Tech. What follows are excerpts of that conversation. SE: Leti recently formed an alliance with Soitec. Under the terms, Leti and Soitec are formin... » read more

Tuesday At DAC 2018


The morning starts with the Accellera Breakfast. Accellera has made some significant progress this year and we can expect to hear about the approval of the Portable Stimulus 1.0 specification later in the conference as well as the initial release of SystemC CCI as well as a proposal for the creation of an IP Security Assurance Working Group, which will discuss standards development to address s... » read more

Silicon CMOS Architecture For A Spin-based Quantum Computer


Source: UNSW Sydney Authors: M. Veldhorst (1,2),  H.G.J. Eenink (2,3) , C.H. Yang (2), and A.S. Dzurak (2) 1 Qutech, TU Delft, The Netherlands 2 Centre for Quantum Computation and Communication Technology, School of Electrical Engineering and Telecommunications,UNSW, Sydney, Australia 3 NanoElectronics Group, MESA+ Institute for Nanotechnology,University of Twente, The Netherlands Te... » read more

Inside FD-SOI And Scaling


Gary Patton, chief technology officer at [getentity id="22819" comment="GlobalFoundries"], sat down with Semiconductor Engineering to discuss FD-SOI, IC scaling, process technology and other topics. What follows are excerpts of that conversation. SE: In logic, GlobalFoundries is shipping 14nm finFETs with 7nm in the works. The company is also readying 22nm FD-SOI technology with 12nm FD-SOI ... » read more

← Older posts