September 2013 - Page 6 of 9 - Semiconductor Engineering

Time To Meet A Patterning Master… An Octopus
By Michael Watts - 12 Sep, 2013 - Comments: 0

Animals that can adaptively camouflage are always rather fascinating, but how about an octopus that sees in black and white and can vary its color and texture? There is a fabulous video clip from Roger Hanlon, senior scientist at Woods Hole Marine Biological Laboratory that found me through various friends (thanks to Facebook). Roger Hanlon said that “when I captured the first scene I started... » read more

Power Optimization Requires Higher-Level Thinking
By Ann Mutschler - 12 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler With consumer demand—much of it for power sensitive mobile devices—driving the bulk of semiconductor design activity, it would seem obvious that the way chips are designed would have changed to reflect that. But have they? From an EDA perspective, the term ‘system level’ is used to mean ‘product level’ but this may not be enough, especially when it come... » read more

Analysis Of Random Resistive Faults And ATPG Effectiveness At RTL
By Various Writers - 12 Sep, 2013 - Comments: 0

The use of register transfer level (RTL) descriptions for design is now commonplace throughout the electronics industry. The wide range of flexibility in both Verilog and VHDL has provided incredible freedom so that the same function may be approached from many different directions. The resulting RTL may meet the functional requirements but fail to meet various other requirements such as optimi... » read more

HotChips: Power8
By Barry Pangrle - 12 Sep, 2013 - Comments: 2

It’s another year, another HotChips Conference and another update on IBM’s POWER processor. IBM continues to impress with its big iron processor, and this year it’s the new POWER8. IBM announced more details of its new POWER8 processor at HotChips and IBM now joins Intel at 22nm, but with the twist that IBM’s process is based on SOI technology. The POWER8 quadruples the thread count ... » read more

The Power Of Low Power
By Ed Sperling - 12 Sep, 2013 - Comments: 0

In the United States, new rules that cars will need to average 54.5 miles per gallon by the year 2025, and 35.5 mpg by 2016, suddenly seem very achievable. In fact, some cars in development are reporting close to an equivalent of nearly 100 mpg, and the numbers are likely to go well into the triple digits. The same kinds of results are showing up in handheld mobile devices, which now have th... » read more

How Secure Are Low-Power Techniques?
By Ann Mutschler - 12 Sep, 2013 - Comments: 0

As a chip designer, you and your team have done the best job possible to optimize power in your SoC, likely utilizing all of the low power techniques at your disposal. The chip tapes out, gets implemented into systems and it’s a success! Then the call comes that your chip has been hacked within the system it’s in and you and your team are left shaking your heads in wonder. I can imagine ... » read more

The IC Supply Chain: The Day After Tomorrow
By Atrenta - 12 Sep, 2013 - Comments: 0

Last month, I wrote about the implications of hacking in a connected world. Judgment Day from the Terminator franchise came to mind. All that paranoia is still “out there” a bit, I admit. Let’s bring it down to a more pedestrian level in this post… Plenty has been written about the disaggregated, distributed, worldwide semiconductor supply chain. Design groups all over the world work... » read more

Five Emerging DRAM Interfaces You Should Know For Your Next Design
By Various Writers - 12 Sep, 2013 - Comments: 0

Producing DRAM chips in commodity volumes and prices to meet the demands of the mobile market is no easy feat, and demands for increased bandwidth, low power consumption, and small footprint don’t help. This paper reviews and compares five next-generation DRAM technologies— LPDDR3, LPDDR4, Wide I/O 2, HBM, and HMC—that address these challenges. To view this white paper, click here. » read more

Analysis Of Random Resistive Faults And ATPG Effectiveness At RTL
By Various Writers - 12 Sep, 2013 - Comments: 0

The use of register transfer level (RTL) descriptions for design is now commonplace throughout the electronics industry. The wide range of flexibility in both Verilog and VHDL has provided incredible freedom so that the same function may be approached from many different directions. The resulting RTL may meet the functional requirements but fail to meet various other requirements such as optimi... » read more

New Risk Factors For SoCs
By Ed Sperling - 12 Sep, 2013 - Comments: 0

By Ed Sperling Third-party IP is becoming increasingly important in SoC designs. It saves development time and adds unique value. It also can improve performance and lower power, because a company specializing in IP frequently can build and optimize it better than a company that builds entire chips. But there are also plenty of landmines in IP integration, and there is a growing concern abo... » read more

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