November 2013 - Page 7 of 10 - Semiconductor Engineering

Are Designers’ X-Analysis Needs Different From Verification Engineers?
By Lisa Piper - 11 Nov, 2013 - Comments: 0

The propagation of unknown (X) states has become a more pressing issue with the move toward billion-gate SoC designs. Besides the sheer complexity of these designs, the common use of complex power management schemes increase the likelihood of an unknown ‘X’ state in the design translating into a functional bug in the final chip. This article describes a methodology that enables design an... » read more

What Color Is That LED?
By Katherine Derbyshire - 11 Nov, 2013 - Comments: 0

As I discovered while researching an upcoming article on phosphors for LED lighting, the question turns out to be surprisingly difficult to answer. Measuring the spectrum of a light source is straightforward, but determining how that spectrum will be perceived by the human eye is more challenging. Under medium and high brightness conditions, the color perceived by the brain will depend on s... » read more

Recycling Electronic Components As Fishing Lures
By Brian Bailey - 08 Nov, 2013 - Comments: 0

I have a regular search set up to help me find interesting and relevant [getkc id="16" comment="patent"] and patent applications within our industry and most of the time they are serious patents. Many come from the large EDA and semiconductor companies, systems houses and some from small startups attempting to protect their nascent technology. But one came up on my search today that was a litt... » read more

User Case Study
By Joseph Hupcey III - 08 Nov, 2013 - Comments: 0

In prior articles I’ve written in general terms of about formally verifying the impact of adding low power control circuitry with Jasper’s Low Power Verification App. At the recent Jasper User’s Group meeting on Oct. 22, a real world case study of this app in action at STMicro’s R&D center in India was presented. Here are some highlights from this paper: DUT in question: an AR... » read more

The Week In Review: System-Level Design
By Ed Sperling - 08 Nov, 2013 - Comments: 0

Si2’s OpenPDK rolled out its Open Process Specification 1.1, including elements necessary to automatically create a process design kit using any EDA vendor’s design flow. The standard uses formal grammar based on the XML Schema Definition. ARM won a deal with Rockchip, which is extending its license to a number of ARM processors as well as its GPU and interconnect technology. This marks ... » read more

The Week In Review: Manufacturing & Design
By Mark LaPedus - 08 Nov, 2013 - Comments: 0

GT Advanced Technologies has entered into a multi-year supply agreement with Apple for sapphire materials. GT will own and operate its furnaces and related equipment to produce the sapphire materials at an Apple-owned facility in Arizona. GT expects to employ more than 700 people in the facility. Apple will provide GT with a prepayment of about $578 million. “We believe Apple likely has signi... » read more

What Do Timing Constraints Have To Do With Clock Domain Crossing?
By Ramesh Dewangan - 07 Nov, 2013 - Comments: 0

As the complexity of designs has scaled, the need for complete and accurate timing constraints (defined typically as Synopsys Design Constraints or SDC) has become extremely critical. High quality timing constraints not only reduce the total effort required to achieve timing closure, but also reduce the number of iterations during that process. In the worst case, incorrect timing constraints ca... » read more

ARM Cortex-A53, UPF & FD-SOI
By Barry Pangrle - 07 Nov, 2013 - Comments: 0

The IEEE Standards Association Symposium on Electronic Design Automation (EDA) Interoperability was held on Oct. 24. I found the first session, Interoperability Challenges: Power Management in Silicon, with presentations by Erich Marschner of Mentor Graphics and Stuart Riches and Adnan Khan (both from ARM) to be particularly interesting. Earlier this year, the IEEE announced a new version of UP... » read more

Low-Power Crisis = Danger & Opportunity
By Brian Fuller - 07 Nov, 2013 - Comments: 0

If you’re a student of these things, you’ve no doubt heard that in Japanese, the word “crisis” is divided equally into “danger” and opportunity.” The biggest opportunity for electronics designers is also their biggest challenge: power management. Ask anyone today and they’ll tell you that minding and managing power consumption and leakage is a big concern. How big? At DAC... » read more

Synopsys ARC HS Processors: High-Speed Licensable CPU Cores for Embedded Applications
By Various Writers - 07 Nov, 2013 - Comments: 0

Synopsys is a leading EDA company with an extensive portfolio of licensable DesignWare intellectual property (IP). The portfolio includes interface IP, analog IP, embedded memories, and logic libraries. Although most chip designers know that DesignWare IP also includes licensable CPU cores and subsystems, many are surprised to learn that Synopsys is second only to ARM in the number of chips tha... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy