January 2014 - Page 4 of 10 - Semiconductor Engineering

The Week In Review: System-Level Design
By Ed Sperling - 24 Jan, 2014 - Comments: 0

India's reliance on technology has created a huge demand for software in the country. IDC expects the market for enterprise software in India to grow 19%, and the market for collaborative applications to grow 13.5%. Growth is continuing across all business markets, turning India into a huge consumer of software rather than just a creator. The enterprise software market in India is dominated by ... » read more

What’s The Backup Plan?
By Ed Sperling - 23 Jan, 2014 - Comments: 0

Over the past dozen years we have witnessed two major breakdowns in the global semiconductor supply chain. The first occurred in 2002, when an outbreak of severe acute respiratory syndrome (SARS) basically closed off Chinese manufacturing for several months. The second major problem occurred in 2011, when the Tohoku earthquake and a devastating tsunami shut down a good portion of Japanese produ... » read more

Printed Electronics Gets Serious About Manufacturing
By Michael Watts - 23 Jan, 2014 - Comments: 0

A leading indicator in the coming-of-age saga of a new technology is the enthusiasm to be in the business of supplying manufacturing infrastructure. To sell infrastructure, there needs to be a belief that there are several customers out there. At the recent IDTech conference for printed electronics, the transition to manufacturing was clear based on those who presented and some notable absences... » read more

Waiting For Next-Generation Lithography
By Mark LaPedus - 23 Jan, 2014 - Comments: 2

Nearly 30 years ago, optical lithography was supposed to hit the wall at the magical 1 micron barrier, prompting the need for a new patterning technology such as direct-write electron beam and X-ray lithography. At that time, however, the industry was able to push optical lithography for volume chip production at the 1-micron node and beyond. This, in turn, effectively killed direct-write e-... » read more

The Bumpy Road To 3D NAND
By Mark LaPedus - 23 Jan, 2014 - Comments: 1

The NAND flash memory market is dynamic, but it’s also sometimes predictable. Suppliers tend to roll out identical NAND flash chips and then scale them to smaller geometries. And NAND chip prices rise and fall, depending on the supply/demand equation at a given point. Going forward, though, the NAND market is expected to become less predictable, if not chaotic, amid a new and major technol... » read more

The Road Ahead for 2014: Semiconductors
By Brian Bailey - 23 Jan, 2014 - Comments: 1

Last week, Semiconductor Engineering examined the 2014 predictions from several thought leaders in the industry and published those predictions that related to general market trends. Many of those predictions require some advances in semiconductor technologies and fabrications capabilities. It is those predictions that will be examined in this part, followed next week by the predictions related... » read more

Executive Viewpoint: Qualcomm On Process Technology
By Mark LaPedus - 23 Jan, 2014 - Comments: 3

Semiconductor Engineering sat down to discuss current and future process technology challenges with Geoffrey Yeap, vice president of technology at Qualcomm. SE: You have pointed out there is a fundamental shift taking place at the 28nm logic node. This is the first node in which mobile chips have been ramped up first within the foundries, ahead of computing-based ICs. Many believe that 28nm ... » read more

The Next Big Threat: Manufacturing
By Ed Sperling - 23 Jan, 2014 - Comments: 0

The business adage that you’re only as good as your partners should be a core principle of doing business when it comes to security. But with a complex SoC you don’t always know all your partners, who financed them—or worse, who else they’re working with or working for. Consider this scenario: A band of sophisticated thieves grinds off the top of an SoC package, inserts probes to map... » read more

The Trouble With Triples—Part 2
By David Abercrombie - 23 Jan, 2014 - Comments: 1

In my last blog, we started to look at some of the challenges of triple patterning (TP) compared to double patterning (DP). In particular, we looked at the algorithmic complexity of determining if a valid coloring solution exists, and if so, producing a three-mask decomposition. This time, let’s look into the challenges of what to do if a layout is not legally decomposable into three colors. ... » read more

Germanium wedge-FETs pry away misfit dislocations
By Katherine Derbyshire - 23 Jan, 2014 - Comments: 1

Any approach to alternative channel integration must consider the lattice mismatch between silicon and other channel materials. Some schemes, such as IMEC’s selective epitaxy, view the lattice mismatch as an obstacle and look for ways to minimize its effects. This point of view certainly has merit: misfit dislocations do significantly degrade transistor performance. Still, back in 2011 Shu-Ha... » read more

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