Waiting For Next-Generation Lithography

The semiconductor industry has several possible replacements for 193nm immersion, but timing and commercial viability are still in question.


Nearly 30 years ago, optical lithography was supposed to hit the wall at the magical 1 micron barrier, prompting the need for a new patterning technology such as direct-write electron beam and X-ray lithography.

At that time, however, the industry was able to push optical lithography for volume chip production at the 1-micron node and beyond. This, in turn, effectively killed direct-write e-beam and X-ray as viable lithographic options for production fabs.

Today, lithographers are asking themselves the same question: Will history repeat itself? In fact, there are some eerie similarities, as well as vast differences, between the 1980s and today. As before, many have predicted the demise of today’s optical lithography. As a result, many see an urgent need for a next-generation lithography (NGL) technology, namely extreme ultraviolet (EUV), multi-beam and nanoimprint.

EUV is basically a soft X-ray lithography technology. Multiple-beam electron-beam is a newfangled version of direct-write e-beam. Nanoimprint is a new take on an old hot embossing technique. Another emerging NGL candidate, directed self-assembly (DSA), is a complementary patterning scheme using block copolymers.

From one perspective, history is repeating itself. Optical-based 193nm immersion lithography continues to extend to finer geometries and remains the workhorse production tool in the fab. And needless to say, EUV, multi-beam and nanoimprint are delayed and not ready for use in volume chip production.

But when comparing the 1980s and today, there are also some striking difference. In the 1980s, the industry broke the 1-micron barrier with a $1 million stepper. Today, chipmakers must pay $50 million or more for a scanner. And the patterning challenges are escalating at the 20nm node and beyond. “Now, companies like Intel are being forced to adopt double patterning techniques, which add masks and other process steps, and are terribly complicated and expensive,” said Weston Twigg, an analyst with Pacific Crest Securities.

And unlike the 1980s, the industry isn’t ready to throw in the towel on NGL—yet. “We definitely have not given up on that,” said Yan Borodovsky, a senior fellow and director of advanced lithography at Intel. “We are still committed to support several technologies under development. This is EUV, e-beam and directed self-assembly. We are paying attention to them and have active efforts in all three of them.”

So what is the status of NGL? And when will the various technologies finally ship?

Moving targets
The shipment schedules for the various NGLs remain difficult to pin down, but clearly the industry needs a solution sooner than later. At 20nm, for example, the foundries will continue to utilize 193nm immersion scanners, but at this node, they are also forced to use new and expensive multiple patterning schemes.

Generally, the foundries will follow the same strategy when they roll out their initial finFET processes at the 16nm/14nm node. The initial finFETs from the foundries will make use of a 20nm backend. All told, there is “no true lithography shrink” at 16nm/14nm, meaning the foundries can use their existing tools, according to Pacific Crest’s Twigg.

At the foundries, the 20nm/16nm/14nm processes could last until 2016 or 2017, Twigg said. The big challenge comes at 10nm, when the foundries must decide whether to extend 193nm/multiple patterning or go with an NGL like EUV. “As foundries migrate to 10nm in 2017 or 2018, they should maintain flexibility to use multiple patterning or EUV—if it is ready,” he said.

Using a 13.5nm wavelength, EUV is attractive because it keeps the industry on a single-exposure path. But EUV has encountered several delays due to the lack of adequate power sources and other issues. “For defectivity, we are 10X away,” said Bryan Rice, senior director of R&D transformation at GlobalFoundries. “That’s a big order of magnitude.”

For this reason and others, EUV could miss the 10nm window. “Right now, the gaps (for EUV) are significant,” Rice said. “So at this point, we’re forced to say for 10nm, we can’t use EUV. We have to choose 193nm.”

EUV is also in jeopardy of missing the 7nm node. For some time, Intel stated it would extend 193nm immersion to 10nm. Then, Intel would insert EUV at 7nm, although there are signs that the chip giant may push out the technology. “For Intel, we expect EUV to be adopted after the foundries, likely at the 5nm node, with a chance for insertion at the 7nm node,” said Pacific Crest’s Twigg.

Intel, in fact, is pioneering a concept called complementary lithography. Based on a 1D layout, complementary lithography involves a two-step process—gratings and line cuts—to pattern designs. The first exposure uses 193nm immersion, which makes the gratings. The remaining exposures are used to cut the pitch-divided lines.

To perform the cut step, Intel is still evaluating EUV, multi-beam and DSA, said Intel’s Borodovsky. “Each of them is on their own path. EUV, hopefully, will be ready before anything else. EUV is on a path of delivering a viable solution, hopefully in 2015 or 2016. Then, if e-beam comes two or three years later, we will have a full complement of tools.”

At present, ASML Holding’s latest goal for EUV is to achieve a throughput of 70 wafers an hour by 2014. “There might be a place for the technology even if source power targets will not be met on time,” Borodovsky said. “There might be a path to mitigate those shortcomings without sacrificing quality.”

Getting direct
For some time, Borodovsky and others have been proponents of another NGL—multi-beam. This technology falls in the category of direct-write lithography, which was pioneered by IBM in the 1980s. Direct-write is attractive because it enables fine resolutions and does not require a costly photomask. But the throughputs for single-beam e-beam are too slow, making it expensive for volume IC production.

Still, direct-write is ideal for IC prototyping and the production of ASICs. “If there is one company in the industry where direct-write e-beam makes sense, it’s us,” said Ronnie Vasishta, president and chief executive of eASIC, a fabless supplier of ASICs.

For example, eASIC has its 90nm devices made using both direct-write and optical lithography. At 90nm, eASIC’s foundry partner is Fujitsu. Fujitsu has a single-beam e-beam tool from Advantest. Meanwhile, at the foundry, eASIC maintains an inventory of pre-processed wafers up to the metal six layer. The bulk of the fabrication process is already completed using traditional optical lithography. The device is then customized at the via layer using direct-write e-beam.

“Our chip is adaptable using a single via,” Vasishta said. “The ability for direct-write e-beam to process that via layer makes sense economically, particularly for prototypes. You don’t build a mask when you are developing the prototype. And then, the prototypes are delivered to customers. The prototype works and goes into production. Then, you would build a mask for that one layer and you would go into production using that mask.”

The company’s 90nm flow has been successful in the market, according to Vasishta, but eASIC is not using direct-write at subsequent nodes. At 45nm and 28nm, eASIC decided to switch foundry partners. “(Fujitsu’s) roadmap for 45nm and 28nm wasn’t really clear at the time when we made those choices,” he said.

Today, eASIC is shipping 45nm ASICs, which are being made on a foundry basis at GlobalFoundries. Meanwhile, eASIC’s upcoming 28nm devices will be made by Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). Both GlobalFoundries and TSMC are separately processing eASIC’s chips using traditional optical lithography, but not direct-write.

“Direct-write e-beam isn’t available in the fabs that we are using for those technologies,” Vasishta said. “We are not using direct-write e-beam any longer, but we could if the fabs supported the tools at advanced nodes.”

On the other hand, the foundries are paying close attention to a souped-up version of direct-write called multi-beam. Using multiple beams, the technology combines the fine resolutions of e-beam with higher throughputs. Advantest, KLA-Tencor, Mapper Lithography, Multibeam and Vistec are separately developing multi-beam tools.

But multi-beam has encountered more delays than EUV. Originally, some vendors promised to ship their systems by 2005, but the first beta-like systems are not expected until 2014. The first production tools are not due out until 2018. “We would like to have them before that,” Intel’s Borodovsky said. “But to be realistic, given the amount of funding that goes into e-beam, and the current commitments, 2018 is when one can think about commercial tools.”

Multi-beam suffers from a multitude of challenges. “Current systems are designed to be general-purpose systems that write very complicated two-dimensional layouts,” Borodovsky said. “Because of that, the tools themselves are very, very complex. This complexity leads to significant technical problems.”

One company, Multibeam, is developing tools specifically for the complementary lithography approach as outlined by Intel. “Tools designed for complementary lithography can be significantly simpler. And because of that, the risk for delay will be smaller,” he added.

In multi-beam, there are various approaches. Another company, Mapper, is developing a 5-kV tool. It consists of an aperture/blanker array that is housed in a column, which promises to project 13,000 beams.

The first beta machine has recently been installed at CEA-Leti. Instead of 13,000 beams, the first tool will consist of 1,300 beams. The goal is to pattern 32nm half-pitch images at one wafer per hour. The other goal is to demonstrate full-field exposure and alignment capability, said Serge Tedesco, lithography program manager at CEA-Leti.

In addition, Mapper is looking at developing a separate and intermediate tool, Tedesco said. Capable of throughputs from six to eight wafers an hour, that system would be targeted for applications besides the leading edge. “A lot of companies are looking at using this type of system for less advanced node, even 65nm, 45nm and 28nm,” he said.

In contrast, Multibeam is developing a system, which uses multiple miniature columns and vector scanning of shaped beams to boost throughput. The company is developing what it calls Complementary E-Beam Lithography (CEBL).

The idea is that a multi-beam tool would pattern only the critical layers. “All of the other layers will be patterned by traditional optical lithography,” said David Lam, chairman of Multibeam. “CEBL could be used to pattern line-cuts in critical layers to complement optical lithography. The critical layers are difficult to pattern with optical. And, of course, they are the most costly because of multiple patterning.”

Still, the NGLs—DSA, EUV, multi-beam and nanoimprint—all have a lot to prove. Nonetheless, chipmakers are still counting on manufacturing technologies like NGL to keep them cost competitive. “The intersection of cost and growth markets is causing so much disruption in the industry right now,” eASIC’s Vasishta said. “We are on a roller coaster ride. So it’s going to be very volatile as to which companies can retain a value proposition to survive and which ones can’t.”


DiogenesCicero says:

As usual, nanoimprint is given short shrift, mentioned in passing, without discussion. It’s inclusion could have triggered a whole new facet of this issue: the potential bifurcation (trifurcation?) of lithography from the heretofore monolithic optical lithography for everything, to quad patterning for logic (with or without DSA) and imprint for nonvolatile memory. At the recent lithographers conference in La Quinta, Toshiba said they planned to use nanoimprint. Why nanoimprint? It’s cheap, and unlike the other NGLs, it has a working source, resist, blanks and masks. Defects and overlay must be improved but those don’t appear to the the showstoppers that source/resist/blanks/masks seem to be for the other NGLs.

[…] uni-directional metal patterns, and then cut line ends into the pattern. This is one embodiment of complimentary lithography. There are many downsides to this approach which will need to be part of said rigorous assessment. […]

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