January 2014 - Page 7 of 10 - Semiconductor Engineering

The Road Ahead For 2014
By Brian Bailey - 16 Jan, 2014 - Comments: 1

Semiconductor Engineering asked several thought leaders in the industry about the market drivers that are affecting their product planning operations for 2014. While almost everyone sees mobile devices continuing to be the major driver during 2014, there are some emerging areas that may start to have a larger impact. This article takes a look at some of those and the impacts they could have on ... » read more

Three Must-Watch Electronics Trends in 2014
By Brian Fuller - 16 Jan, 2014 - Comments: 0

It’s halfway through January, and I think we’ve exhausted our “2014 Forecast” posts for the year. Still, it’s helpful to consider what lies ahead when all we have under our belts at this point is CES 2014 (and that event was clearly underwhelming as a technology bellwether). I propose three areas to watch closely in 2014, based on ploughed ground from some excellent industry observ... » read more

Power Grid Analysis—Challenges At 20nm And Below
By Christen Decoin - 16 Jan, 2014 - Comments: 1

Introduction The need for power grid analysis (PGA) emerged in the early 2000s, when leading-edge semiconductor companies were starting 90nm designs that unveiled new technical challenges. Since then, PGA has coped with diverse challenges for each new technology node, including coverage (dynamic PGA emerged in the mid-2000s), performance, and capacity (a bottleneck at the 32/28nm node). But 20... » read more

Using USB 3.1’s Multiple INs To Reach 10 Gbps Data Rates
By Matthew Myers - 16 Jan, 2014 - Comments: 0

In January 2013, the USB-IF announced USB 3.1, a new generation of the protocol that will double USB 3.0 data throughput performance to 10 Gbps. In addition to this increased speed, the specification requires compatibility with existing cables, connectors, software stacks, and device class protocols. USB 3.1 products must support existing 5 Gbps and new 10 Gbps hubs and devices, as well as olde... » read more

Verifying Power Optimized Designs Using Sequential Analysis
By Rob Eccles - 16 Jan, 2014 - Comments: 0

All power optimization tools can perform combinational optimization, where there is an opportunity to gate a register clock input, based on the combinational logic that is feeding the register’s data input. While this method works well and does not alter the logic behavior at the register, the problem is that it leaves additional power saving opportunities on the table. However, sequential... » read more

Power Noise And Reliability Sign-off For The Sub-20nm FinFET Era
By Aveek Sarkar - 16 Jan, 2014 - Comments: 1

There is a greater focus on power noise and reliability simulations and sign-off as the complexity of SoC designs continue to increase with 100+ different voltage islands, clock and power gating techniques, and multiple IPs each operating on different clock and power domains, etc. The technology node migration from 40nm to 20nm is driving requirements for electro-migration (EM) and reliability ... » read more

Power Resolutions For 2014
By Mark Baker - 16 Jan, 2014 - Comments: 0

As the ball dropped at midnight in New York’s Time Square, signifying the beginning of 2014, many had already decided on their resolutions for the New Year. Others decide during the first few days of the New Year. Undoubtedly, consideration involves common resolutions that we fall back on year after year. Individuals might think about health, losing weight and becoming more fit. Others think ... » read more

Simple Does Not Mean Easy
By Ann Mutschler - 16 Jan, 2014 - Comments: 0

When it comes to chip design we speak constantly about managing complexity - how best to architect for it, how to manage it, what design techniques to use, what the impact on the system will be etc. - but we don't speak too much about making the design more simple. Instead, we heap on more complexity to manage the complexity. As with everything else in life it seems just because something is... » read more

Tech Talk: Dealing With The Unknowns
By Ed Sperling - 15 Jan, 2014 - Comments: 0

Rebecca Lipon, senior product marketing manager for verification at Synopsys, discusses the problematic X's and where verification teams typically make mistakes in trying to eliminate the false X's from their designs. Power emerges as the biggest problem. [youtube vid=Iym4ITWJJrs] » read more

Power Delivery Network (PDN) Verification Coverage
By Various Writers - 15 Jan, 2014 - Comments: 0

This paper presents a methodology for comprehensive power grid verification coverage, including identification of power grid weaknesses early in the design cycle. To download this white paper, click here. » read more

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