April 2014 - Page 2 of 10 - Semiconductor Engineering

Defects And Contamination Control
By Michael Watts - 24 Apr, 2014 - Comments: 0

This week’s episode of the new Cosmos was particularly interesting because Neil Degrasse Tyson filled in a part of the recent history of semiconductors and made a great point about ethics in science. I had just moved to the United States when Carl Sagan’s Cosmos first aired, and at the time I thought he connected all sorts of interesting dots. The new edition is even better. In this ... » read more

Follow The Investments
By Ed Sperling - 24 Apr, 2014 - Comments: 0

Where is design heading over the next few years. The best way to tell that is to find out where the development dollars are going, and foundries and tools always precede actual designs. The foundries are starting to spend money—lots of it—on finFETs and 28nm. And while they’re talking about 2.5D and 3D, the money isn’t going there just yet. In fact, there are two different processes ... » read more

What Are EDA’s Big Three Thinking?
By Ed Sperling - 24 Apr, 2014 - Comments: 4

Over the past six weeks, the CEOs of Cadence, Synopsys and Mentor Graphics—in that order—have delivered top-down visionary messages to their user groups. Semiconductor Engineering had the opportunity to attend all three sessions, and has compiled comments from each on a variety of subjects. In some cases, all the CEOs were in sync. In others, they were not. In still others, it was difficult... » read more

Graphing Toward Standardization
By Brian Bailey - 24 Apr, 2014 - Comments: 0

Graph-based verification has become the hot topic of the day. It commanded a lot of attention at the recent DVCon, promises to fix many of the problems plaguing functional verification, can provide an automated way to perform system-level verification, enables portability of tests between simulation, emulation and prototyping, reduces the wastage created by constrained random test pattern gener... » read more

How To Improve Debug Productivity
By Ann Mutschler - 24 Apr, 2014 - Comments: 0

In the realm of SoC verification world, it often takes a very short amount of time to write the testbench and the code, and the rest of the time — up to 90% — is spent debugging. After all, verification is essentially finding the bugs in a design. Debugging essentially has evolved over the years on the same path and complexity curve as design. Now debugging needs to evolve to keep pace, ... » read more

Efficiency Metrics Get Fuzzy
By Ed Sperling - 24 Apr, 2014 - Comments: 0

Not too long ago chipmakers used to measure transistors per hour and software developers would measure lines of code written per day or per week. Those metrics have fallen by the wayside—and chipmakers are still lamenting that loss. The problem is that nothing has come along to replace the old metrics, and complexity has left many chipmakers scratching their heads about how to build effici... » read more

Extending UVM To Analog
By Ann Mutschler - 24 Apr, 2014 - Comments: 2

As SoC complexity has grown, so too has the need to model the analog/mixed-signal content in a similar way as the digital content to make simulation easier. One way to do this is within the context of the Universal Verification Methodology (UVM). In fact, this can and is being done today with UVM as it stands, according to a number of industry sources. However, there is also growing interest... » read more

The Fading Art of Person-to-Person Communication
By Mike Gianfagna - 24 Apr, 2014 - Comments: 0

Have you ever sat in your cube at work and received an email from the person sitting next to you? Have you watched your kids text their friends when they’re all in the same room? Face it, typing is replacing talking. All this always-on technology is contributing to the demise of simple, person-to-person communication. I sometimes wonder if future generations of well-to-do people will hire pro... » read more

SoC Assembly And IP Reuse
By Kurt Shuler - 24 Apr, 2014 - Comments: 2

I had the honor and opportunity to present at the 2014 Electronic Design Process Symposium in Monterey last Friday. This annual workshop is run by the IEEE Computer Society of Silicon Valley and the IEEE Council on Electronic Design Automation. There were more than 30 participants each day. Most of them very experienced people with lots of technical and business responsibilities. It was ... » read more

Does Formal Have You Covered?
By Brian Bailey - 24 Apr, 2014 - Comments: 1

In part one of this roundtable, the panelists talked about the recent changes that have brought formal to the forefront of verification and discussed the challenges that the UVM have brought to formal. In this segment we start exploring those difficulties in more detail and the progress made with integrated coverage. Participating in the panel were Pete Hardee, director of product management fo... » read more

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