November 2015 - Page 4 of 10 - Semiconductor Engineering


Measuring FinFETs Will Get Harder


The industry is gradually migrating toward chips based on finFET transistors at 16nm/14nm and beyond, but manufacturing those finFETs is proving to be a daunting challenge in the fab. Patterning is the most difficult process for finFETs. But another process, metrology, is fast becoming one of the biggest challenges for the next-generation transistor technology. In fact, [getkc id="252" kc_n... » read more

Packaging Wars Ahead


There has been much talk about semiconductor industry consolidation, but the shift into advanced packaging could have more far-reaching effects than all the mega-deals so far. Packaging is big business. Yole Développement has pinned the market at $30 billion, but that's only a thin slice of the pie that's in play. Companies that win the packaging deals also have a good shot of winning the m... » read more

Inside X-ray Metrology


Chipmakers are ramping up a new class of chip architectures, such as 3D NAND and finFETs. Measuring and characterizing the tiny structures in these technologies is a major challenge. It will not only take the traditional metrology tools, but also various X-ray techniques. To get a handle on X-ray metrology, Semiconductor Engineering recently discussed the trends with the following experts: ... » read more

Inside Multi-Beam E-Beam Lithography


Semiconductor Engineering sat down with David Lam, chairman of Multibeam, a developer of multi-beam e-beam tools for direct-write lithography applications. Lam is also a venture capitalist. He founded Lam Research in 1980, but left as an employee in 1985. What follows are excerpts of that conversation. SE: How has the equipment business changed over the years and what’s the state of the i... » read more

The Growing Role Of Extended Supply Chain Collaboration


At the executive keynote panel held at Semicon West 2015, one of the key industry challenges discussed was the growing need for closer collaboration between supply chain partners in order to support the fast time to market and shortened product lifecycles of today’s consumer electronics. Traditionally, the yield ramp phase has been a critical time to resolve manufacturing issues, enable high ... » read more

What Comes Next


By Marc Heyns I’m very optimistic about the continuation of Moore’s Law. But in saying that, I’m speaking about Moore’s Law purely as an economic law. I believe we’ll be able to offer increasing amounts of functionality at lower and lower costs. And technological innovations as well as advances in design and application will be crucial in realizing this. But I don’t believe a ... » read more

ReRAM Gains Even More Steam


The prospect of using the latest in finFET processing to enable embedded non-volatile memory (NWM) will be described by a team from TSMC and Tsing Hua University in Taiwan at the IEDM meeting on Dec. 8 in Washington, D.C. Embedded NVM has been the first commercial application of ReRam, with products from Panasonic and Terrazon. Industry leaders agree the creation of NVM as a seamless additio... » read more

What’s Really Causing Line-Edge Roughness?


As previously discussed, shot noise is an important contributor to line edge roughness. However, as the title of one paper on the subject put it, “Do not always blame the photons.” The line edge roughness of a chemically amplified resist ultimately depends on photoacid generation and the deprotection of the resist’s base monomers. Photons absorbed by the resist simply trigger a chain ... » read more

The Silicon Foundry Market Is Alive And Well


I attended the ARM TechCon conference in Santa Clara last week and met with the GlobalFoundries team to discuss their new 14nm finFET technology. GlobalFoundries’ 14LPP technology offering was qualified in the third quarter of 2015 and is on track for volume production in 2016. FX-14 design kits are available to customers now.  This announcement was the culmination of an extensive body of... » read more

Analog Design And Pattern Matching: A Perfect Pairing


While automated pattern matching is widely used in the digital IC physical verification process, adoption in the analog space has been much slower. In fact, the very nature of customized analog circuits lends itself ideally to some of the newer physical verification techniques offered by automated pattern matching technology, enabling designers to reduce verification time while still ensuring d... » read more

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