January 2016 - Page 3 of 10 - Semiconductor Engineering

Power/Performance Bits: Jan. 26
By Jesse Allen - 26 Jan, 2016 - Comments: 0

New switchable material Two MIT researchers developed a thin-film material whose phase and electrical properties can be switched between metallic and semiconducting simply by applying a small voltage. The material then stays in its new configuration until switched back by another voltage. The discovery could pave the way for a new kind of nonvolatile memory. The findings involve the thin-... » read more

Manufacturing Bits: Jan. 26
By Mark LaPedus - 26 Jan, 2016 - Comments: 0

Giant vice Deutsches Elektronen-Synchrotron (DESY), a research center within the Helmholtz Association, has installed a giant vise or press in its organization. The vise, dubbed the Large Volume Press (LVP), measures 4.5 meters in height and weighs 35 tons. It can exert a force of up to 500 tons on each of its three axes. [caption id="attachment_25030" align="alignleft" width="160"] Th... » read more

Inside Neuromorphic Computing
By Mark LaPedus - 25 Jan, 2016 - Comments: 2

Semiconductor Engineering sat down to talk about neuromorphic technology with Guy Paillet, chief executive of General Vision. The fabless IC design house is a pioneer and supplier of neuromorphic chips. What follows are excerpts of that conversation. SE: In 1993, you invented and co-patented a neural networking chip with IBM. Then, you joined General Vision in 1999. Briefly tell us about Gen... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 22 Jan, 2016 - Comments: 0

Samsung Electronics announced that it has begun producing the industry’s first 4-gigabyte DRAM package based on the second-generation High Bandwidth Memory (HBM2) interface. The 4GB HBM2 package is created by stacking a buffer die at the bottom and four 8-gigabit core dies on top. These are then vertically interconnected by TSV holes and microbumps. A single 8Gb HBM2 die contains over 5,000 T... » read more

The Week In Review: Design/IoT
By Jesse Allen - 22 Jan, 2016 - Comments: 0

Tools Synopsys unveiled its comprehensive standard cell library characterization and QA solution, SiliconSmart ADV, highlighting a simple multi-core licensing scheme for easy adaptation to constantly changing characterization workload requirements. Cadence updated its Sigrity portfolio focusing on multi-gigabit interfaces, including automated support for IBIS-AMI model creation, channel m... » read more

Industry Road Map Under Construction
By Ed Sperling - 21 Jan, 2016 - Comments: 0

While most engineers think in terms of PPA—the classic power, performance and area tradeoffs—their bosses tend to see the world in terms of risk vs. opportunity. Until 22nm, these two objectives moved forward at roughly the same pace, despite the growing technical challenges of fitting more functionality into an SoC. Much has changed since then, and even more will change over the next f... » read more

Neuromorphic Chip Biz Heats Up
By Mark LaPedus - 21 Jan, 2016 - Comments: 0

It’s no secret that today’s computers are struggling to keep up with the enormous demands of data processing and bandwidth, and the whole electronics industry is searching for new ways to enable that. The traditional approach is to continue to push the limits of today’s systems and chips. Another way is to go down the non-traditional route, including an old idea that is generating stea... » read more

Why Use A Package?
By Ed Sperling - 21 Jan, 2016 - Comments: 0

Subramanian Iyer, distinguished chancellor's professor in UCLA's Electrical Engineering Department—and a former fellow and director of the systems scaling technology department at IBM—sat down with Semiconductor Engineering to talk about the future of chip scaling. What follows are excerpts of that conversation. SE: Advanced packaging is being viewed as a way to extend scaling in the fut... » read more

5nm Fab Challenges
By Mark LaPedus - 21 Jan, 2016 - Comments: 2

At a recent event, Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel’s nanowire FET, sometimes called a gate-all-around FET, is said to meet the device require... » read more

The Internet Of Power Also Benefits From Moore’s Law
By Imec - 21 Jan, 2016 - Comments: 0

By Jef Poortmans It may sound strange, but striving to achieve smaller dimensions with Moore’s Law is an important enabler for producing increasingly better solar cells, with a more elaborate technology toolbox (including ALD, epitaxy, etc.) Improved process steps are constantly being developed to achieve these small transistor dimensions (for growing material layers or to etch away str... » read more

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