February 2016 - Page 6 of 10 - Semiconductor Engineering


Power/Performance Bits: Feb. 16


Energy storage on microchips After more than half a decade of speculation, fabrication, modeling and testing, an international team of researchers from Drexel University in Pennsylvania and Paul Sabatier University in Toulouse, France, confirmed that their process for making carbon films and micro-supercapacitors will allow microchips and their power sources to become one and the same. Si... » read more

Why Power Modeling Is So Difficult


Power modeling has been talked about for years and promoted by EDA vendors and chipmakers as an increasingly important tool for advanced designs. But unlike hardware and software modeling, which have been proven to speed time to market for multiple generations of silicon, power modeling has some unique problems that are more difficult to solve. Despite continued development in this field, po... » read more

The Week In Review: Manufacturing


SUNY Polytechnic Institute (SUNY Poly) and GlobalFoundries announced the establishment of a new Advanced Patterning and Productivity Center (APPC). The $500 million, 5-year program will accelerate the introduction of extreme ultraviolet (EUV) lithography technologies into manufacturing. The center is located at the Colleges of Nanoscale Science and Engineering (CNSE) in Albany, N.Y. -------... » read more

The Week In Review: Design/IoT


Imagination's Sir Hossein Yassaie stepped down as Chief Executive, and Andrew Heath, one of the non-executive directors, has been appointed Interim Chief Executive. As part of a major restructuring, the company will also sell Pure, its consumer electronics business. Mentor Graphics' Embedded Linux platform has been updated to Yocto 2.0 and expanded to include new security enhancements and ad... » read more

Will 3D-IC Work?


Advanced packaging is becoming real on every level, from fan-outs to advanced fan-outs, 2.5D, and 3D-ICs for memory. But just how far 3D and monolithic 3D will go isn't clear at this point. The reason is almost entirely due to heat. In a speech at SEMI's Integrated Strategy Symposium in January, Babek Sabi, Intel corporate VP and director of assembly and test technology development, warned t... » read more

Debug Becomes A Bigger Problem


The EDA industry has invested enormous amounts of time and energy on the verification process, including new languages, new tools, new class libraries, new methodologies. But the one part of the cycle that defines that type of automation is debug. Development teams are spending half of their time in the debug process and the problem is growing. Part of the reason is that design and debug are... » read more

Adventures In Assembly


With so few [getkc id="81" kc_name="SoC"] designs — if any — today designed completely new from the ground up, the assembly task is an extremely important one to get right. [getkc id="43" kc_name="IP"] components must be put together optimally and efficiently to perfectly match the application requirements, which is complex and intricately nuanced. How companies approach IP varies signif... » read more

Working With FinFETs


One of the key technology trends driving semi-conductor industry is the adoption of finFET processes. As opposed to a traditional planar transistor, the finFET has an elevated channel or “fin,” which the gate wraps around. Due to their structure, finFETs generate much lower leakage power and allow greater device density. Compared to planar transistors, finFET operate at a lower voltage and ... » read more

Thermal Damage To Chips Widens


Heat is becoming a much bigger problem for semiconductor and system design, fueled by higher density and the increasing use of complex chips in markets such as automotive, where reliability is measured in decade-long increments. In the past, heat typically was handled by mechanical engineers, who figured out where to put heat sinks, fans, or holes to funnel heat out of a chassis. But as more... » read more

Automating Coverage And Analysis Of Low Power Designs


There are some exciting new things in the just released IEEE1801-2015 (aka UPF 3.0), some of which have significant benefits for coverage of low power designs, which is what we’ll be looking at in this blog. One of these is improved semantics for the add power state command, introduced in IEEE1801-2009 (aka UPF 2.0). These clarifications to the add power state command allow you to clearly ... » read more

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