20nm IP Portability Appears Virtually Impossible

Moving IP to any design in any foundry is becoming less and less possible at advanced process nodes.


By Ann Steffora Mutschler
Each node on the deep submicron path has brought new challenges to engineering teams, and 20nm is no different. With EUV (extreme ultraviolet) lithography challenges still being worked out, double patterning (DP) instead will be embraced in the manufacturing process most likely until 10nm. Due to the unique nature of DP, IP portability between foundries will become a thing of the past for most SoC design teams, and so will portability between designs.

Specifically, the ability to randomly add in new IP or substitute IP will be severely limited because the DP coloring constraints have a lot of interaction problems between cells, explained David Abercrombie, program manager for advanced physical verification methodologies at Mentor Graphics. “If the cells don’t follow the same methodology in regard to coloring boundary conditions in something as simple as an IP library of standard cells, and they know the cells are going to butt each other (share the power and ground), then because they have to be colored you can’t allow the power rail in one cell to be on mask zero and the power rail on the next cell to be on mask one. They have to end up on the same mask. So you need to enforce that all the powers have a certain coloring and all the grounds have a certain coloring.”

That all works fine in theory until someone else designs an IP library and make all of theirs zeroes. The two of those cannot be combined together. And as with all new processes, the design rules and process details are not clear.

“I’ve heard two schools of thought,” said Manoj Chacko, product marketing director at Cadence. “One school says everything will be decomposed from a cellblock IP level and designers will have to work with decomposed layouts. There is another school of thought saying, ‘Meet our rules, don’t worry about decomposing it, go through your traditional flow but you have to meet all these additional double patterning rules in addition to the traditional design rules. When you come to the end there are qualified double-patterning decomposition tools/engines that all the EDA vendors have. They can decompose it, and then there is a small iterative cycle just to ensure that you have no issues and conflicts and that this is all compliant with what the foundry has.”

But this hasn’t just happened overnight. Hans Bouwmeester, director of IP engineering at Open-Silicon, said that at 40nm, we started seeing limitations on what we could do related to the memories. “In 28nm you see more of those limitations requiring a single poly direction for the entire chip. Portability of IP becomes more and more a concern especially when it concerns analog IP. It doesn’t scale well so you don’t get the area benefits going to the deeper submicron process. So it is definitely a factor that comes more and more into play as we go into deep submicron processes.”

Since 65nm, Jean-Marie Brunet, marketing director for DFM products at Mentor Graphics, has observed a fundamental shift with respect to IP design. In the past, IP designers used to create their IP without regard to where it was going to be used and in what context. Now, with DFM lithography proximity effects, IP vendors have to design their IP knowing it will be used in context No. 1 with one chip and context No. 2 with a different chip. “Unfortunately with advanced nodes, optical radius and OPC effects, the context started to severely affect the intrinsic behavior of the IP. And that is a fundamental shift. They have to make the IP very context free, which is very difficult.”

These contextual issues call for examination of the lithography context to an IP, such as CMP effects, and analysis of contextual problems. The contextual issues get more intense the smaller the node.

Due to contextual issues and other challenges, IP re-use at 20nm with double-patterning will be very complicated. “There’s no question that at 20nm and below those are going to be very different nodes. Design flow, design methodology that we are working on right now, as well as other competitors, is going to be very difficult. I’m not too sure yet if the industry has found an easy way to do IP re-use with double-patterning. We are all going through test chips right now, validation vehicles for reference flows, and re-use of blocks. And each time we are struggling,” Brunet said.

“Solutions are being put together, but I will not say this is a done deal. We will go through issues with double-patterning. Unfortunately, it is going to be very high in cost–not only in mask and silicon, but in design flows as well. I think we’re going toward actually having severe limitations on the type of design styles and rules just because of the nature of double-patterning,” he added.

With each more advanced manufacturing node, the problem will be significantly more painful for tier-two and tier-three SoC developers, as industry players discuss in this video.

Open-Silicon’s Bouwmeester is a bit more optimistic about IP portability in the future. “I’m not completely sure whether it is going to be completely a thing of the past, but I would certainly agree that the expenses IP vendors have to take in order to port IP between foundries are going up. There is more work involved for them to bring a piece of IP they may have for example in a TSMC 28nm process to Global Foundries, and that is expected to continue or become worse as we go to more deep submicron processes. I guess there also may be more business considerations in that TSMC being the lead foundry is getting more and more protective to prevent other foundries from copying parts of their process. In other words, TSMC has a business interest in making it harder to support portability between foundries.

But Abercrombie insisted, “Even though IP vendors would sell you a library for one foundry versus a library for another foundry, honestly, we all know under the hood they built one library and it took the least common denominator. The rules were close enough that just being a little bit intelligent you could make a set that would run on either one. At 20nm and below, no. We talk to these guys and they have to build completely different, from-scratch libraries. There’s no possible way to make one. It says portability is out the window.”

It’s not all bad news, though. Navraj Nandra, senior director of marketing for analog/mixed-signal IP at Synopsys said, “If you are doing libraries and IP development you have to nowadays be early with the technology such that when customers are ready to work in these new nodes they see a bunch of IP available. We see some of these stresses early on. Some of the customers I’m speaking to at the moment are scoping out their 20 nm options—for the ones that are considering 20 nm.”

While he recognizes that IP development complications with 20nm are at least twice the complications of 28nm, he pointed out, “That’s my problem but it’s not my customer’s problem. My customers don’t care. All they care about is making sure schedules and performances are met.”

Walter Ng, vice president of GlobalFoundries’ IP ecosystem, acknowledged there is fear surrounding IP portability at 20nm. “We do see a good amount of concern among the design community with regard to the impact of double patterning on each of them and what it will mean to them and how much it will increase the complexity and difficulty of their task. We are always sensitive to that. In this case, as we go down the technology curve, it’s going to be more and more challenging to achieve the entitlement that maybe over many of the technology nodes previously has just been an expectation.”

“Double-patterning is the only way at this point that we or anybody else can achieve the 2X density that is expected. And we certainly are trying to minimize the requirement because it goes back to balance. We understand the economics of this in addition to the technical challenges, and we are trying to minimize the double-patterning requirements such that it can stay an economically viable technology node both from a processing cost as well as a design cost,” he continued.

As such, GlobalFoundries does real-time collaboration with the top EDA companies, as well as major IP providers.

On top of double patterning, Ng agreed that from an IP portability standpoint 20nm brings another challenge. “The reality among the design community is that even at 28nm, its been very challenging with regard to wanting to preserve portability where it wasn’t intended from the outset.”

“If you want to achieve optimal IP implementation, even if you wanted to try to look at a superset approach and be satisfied with ‘fat’ IP, it hasn’t been easy,” he said. “We have whittled away at the ability to easily port unless it is by design. When it comes to double-patterning and 20nm it certainly ups the bar, and it does make IP portability across random manufacturers a nearly impossible task because of certain aspects of the process definitions as well as the decomposition rules themselves. It’s not going to be the same. With the level of detail, unless it is planned for up front by design, it will be virtually impossible.”

However, he concluded, “It starts subtracting from the value statement of moving to that next technology node. If you’re going to do that superset where you’re not taking advantage of optimizing your IP and optimizing your design for a specific technology node, then you really should be considering whether you should be moving to that node because you’re just leaving so much on the table.”