Synopsys adds IP for 40nm Mie Fujitsu LP process; Rambus wins cryptography key management deal; Cadence wins emulation deal; Diodes to buy Pericom.
IP
Synopsys rolled out logic library and embedded memory IP for the Mie Fujitsu 40nm low-power process. The process has 50% lower power consumption compared with previous process technologies.
Deals
Rambus‘ Cryptography Research Division won a deal to run the Secure Content Storage Association‘s cryptographic key management center. The keys are used in SCSA-enabled devices for securing video content.
MightyWorks ported its microphone processing technologies to Cadence‘s Tensilica DSPs to reduce ambient noise and focus sound in the desired direction. In addition, Israel’s Altair Semiconductor adopted Cadence’s emulation platform for IoT SoC development.
Money
Synopsys replenished its stock repurchase authorization, raising the limit back to $500 million.
M&A
Diodes, which makes standard discrete products, said it would acquire Pericom Semiconductor for $400 million to bolster its analog and mixed signal lines. Diodes reported $891 million in revenue in 2014, while Pericom, which makes switches and timing products, reported revenue of $129 million in the same period.
30 facilities planned, including 10/7nm processes, but trade war and economic factors could slow progress.
Leaders of three R&D organizations, Imec, Leti and SRC, discuss the latest chip trends in AI, packaging and quantum computing.
Applied Materials’ VP looks at what’s next for semiconductor manufacturing and the impact of variation, new materials and different architectures.
What could make this memory type stand out from the next-gen memory crowd.
Researchers digging into ways around the von Neumann bottleneck.
Chips will cost more to design and manufacture even without pushing to the latest node, but that’s not the whole story.
This will go down as a good year for the semiconductor industry, where new markets and innovation were both necessary and rewarded.
Researchers digging into ways around the von Neumann bottleneck.
The term creates hope for some, fear for others, and confusion for all.
While CPUs continue to evolve, performance is no longer limited to a single processor type or process geometry.
Optimizing complex chips requires decisions about overall system architecture, and memory is a key variable.
Why data scrubbing and social issues could limit the speed of adoption and the usefulness of this technology.
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
Leave a Reply