There are now a total of seven published 3D standards.
Since its formation in December 2010, the SEMI 3DS-IC Standards Committee has made significant progress in establishing key standards in areas such as TSV metrology, glass carrier wafers, and terminology. The committee’s two newest standards are SEMI 3D6-0913 – Guide for Chemical Mechanical Planarization (CMP) and Micro-Bump Processes for Frontside Through Silicon Via (TSV) Integration, and SEMI 3D7-0913 – Guide for Alignment Mark for 3DS-IC Process. The addition of these two new standards brings the total number of published SEMI 3D standards to seven.
SEMI 3D6-0913 defines the specifications for middle end of line (MEOL) process related manufacturing flow. In order to speed up volume production of 3DS-IC products, a generic middle-end process flow is needed to communicate the frontend and backend processes. The document focuses on the middle-end process on wafers with or without through silicon via (TSV), including post final metal temporary bonding, wafer thinning, TSV formation and reveal, micro-bumping (UB), redistributed line (RDL) formation and carrier de-bond. Processes commonly used in the production of 3DS-ICs are discussed in SEMI 3D6-0913.
Acceptable CMP criteria of TSV in terms of dishing, erosion, and voids are defined in SEMI 3D6-0913, with the goal of better TSV connectivity as a result of higher CMP quality. SEMI 3D6-0913 also provides measurement methodology for micro-bump dimensions, including sampling rate, sampling sites and mapping, reference datum, and survey available metrology tools. This will improve communication among IC design firms, fabs, and packaging houses. A generic process flow for frontside TSV formation is also described in the standard.
SEMI 3D7-0913 defines alignment mark specifications for 3DS-IC processing. The defined alignment mark specifications including the shape, dimension, and position in this document will be beneficial for the yield of stacking of chip to chip (C2C), chip to wafer (C2W) and wafer to wafer (W2W) 3DS-IC products.
Both of the new Standards were developed by the Taiwan 3DS-IC Middle End Process Task Force. Another group, the 3DS-IC Testing Task Force, seeks to enhance manufacturing yield by developing specifications for electrical testing of prebond and bonded wafers/devices. Their first standard under development is document5485, Guide for Incoming/Outgoing Quality Control and Testing Flow for 3DS-IC Products.
While 3D-IC standardization efforts initially started in North America, a counterpart chapter in Taiwan was formed shortly thereafter and is highly active, as shown above. Interest is also growing in Japan, with activity formally taking place in the Packaging Committee’s Thin Chip (Die) Bending Strength Measurement Task Force. While some chip wafer strength metrology has been standardized, as wafer and chip thickness becomes thinner and thinner, thicknesses under 50um require specialized tools and can be difficult to measure. To rectify this issue, the group is working on a new bending strength measurement method (“Cantilever Bending Method”) for ultra-thin die. The method will be easily described in requirements and specifications among multiple suppliers and result in smooth handling through the supply chain. The Task Force is currently preparing test samples with various wafer thicknesses down to 10um for the experiment of bending strength measurement. Japan is also considering the possibility of the standardization of W2W and D2D Handling.
SEMI 3D standardization meetings take place throughout the year. The North America chapter met in October to continue its work, which is currently spread over three Task Forces: Bonded Wafer Stacks, Inspection & Metrology, and Thin Wafer Handling. SEMI North America efforts have resulted in five published standards to date. To get involved, please contact your local SEMI Standards staff or visit: www.semi.org/standards.
Published SEMI 3DS-IC Standards
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