Just how real is 3D stacking and what are the main hurdles that need to be solved.
Semiconductor Manufacturing & Design examines the myth and reality of 3D stacking–and the hurdles that still need to be solved. In the hot seat: VC Jim Hogan; eSilicon’s Prasad Subramanian; Sonics’ Drew Wingard; Atrenta’s Mike Gianfagna, and Mentor Graphics’ Michael White.
Rising costs and gaps in equipment emerge as technology scales; new tools under development.
Experts at the Table, part 1: Shrinking features isn’t enough anymore. The big challenge now is how to achieve economies of scale and minimize complex integration issues.
Explosion of data is forcing significant changes in where processing is done.
New market opportunities and global competitiveness are limited by qualified people.
Researchers digging into ways around the von Neumann bottleneck.
The promise of advanced packaging is being able to integrate heterogeneous chips, but a lot of work is needed to make that happen.
Better algorithms and more data could bolster adoption, particularly at advanced nodes.
30 facilities planned, including 10/7nm processes, but trade war and economic factors could slow progress.
New architectures, packaging approaches gain ground as costs increase, but shrinking features continues to play a role.
Improvement still needed for uptime, defectivity, line edge roughness and process flows.
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