3D’s Disruptive And Less-Disruptive Sides

The momentum behind vertical stacking of die, either in 2.5D or 3D configurations, is growing. So is the argument about just how big a change this will actually represent.

To a large extent, it all depends on where you’re sitting. Xilinx CTO Ivo Bolsens calls 3D stacking a disruptive technology. From an FPGA standpoint, which potentially could be used as a programmable addition to any SoC, this represents a huge shift—and opportunity. It’s an entry point into the fast lane that previously was dominated by ASICs, with performance and power overhead muted by shorter distances and wide I/O connections to memory chips.

For EDA vendors, the real upside of 3D is around the edges of the technology, and in the potential that new customers will require new tools. Mentor’s push into 3D test is a case in point. Cadence’s integration push will likely fit into this scenario, as well. And the push by Synopsys deeper into the IP world will likely find new growth potential in 3D. There’s also an opportunity for exploring everything from thermal impacts of different IP to 3D topographical layout tools. But the real hope in EDA is that when companies begin putting together 2.5D and 3D packages based on pre-integrated blocks of IP, or possibly even fully integrated die, that complexity will drive customers to start buying more advanced tools.

For the supply chain as a whole, 3D offers a new challenge. It’s a matter of working with partners more closely than in the past—possibly new partners—to deal with more choices and significantly more complexity. This is easier said than done, because understanding a partner’s real strengths won’t be apparent until stacking die becomes a more mature solution. There are risks inherent in any partnership, and there are costs of going to market even with the right partners. But with stacked configurations, those costs are multiples of what they might be in 2D layouts.

–Ed Sperling