7 Ways to Assess Semiconductor IP Quality

Design teams today are struggling with the quality of semiconductor intellectual property. These teams want first-pass success for SoC creation, but that is becoming increasingly difficult to achieve—especially with highly configurable IP. Yet the more configurable the IP is, the more desirable it is as a differentiator. And if not developed correctly, it may be even more risky than non-configurable IP, especially in terms of time to market.

Therefore, it is imperative that an IP is thoroughly verified before it is integrated. The initial cost of configurability pales in comparison to the cost of slowing down a tapeout.

In Figure 1 above, the process of identifying IP quality is long and arduous and most of the responsibility falls on the IP vendor, not the semiconductor design team customer.

Thorough verification can be achieved through seven steps.

In addition to these verification steps, it is important to understand whether your IP has been implemented in high volume SoCs, which means it has been verified at multiple design and production levels. Any team that implements IP not meeting these seven steps is putting their project at risk of the lengthy schedule push outs that cause SoCs to be irrelevant to the market once they finally tape out.

Trust but Verify through 7 Steps:

1. Unit-level. This foundational level is critical to the process because bugs or issues found here will result in problems at subsequent levels.
2. Module-level. If an IP vendor doesn’t offer results of this level to customers, then the design team should think twice about using it. Module level verification is generated during actual user configuration, and it will be implemented in the SoC based on required performance parameters and topology. At this level, the configurable IP mates with the functionality of others in the design. It should be verified by the vendor first, and based on design examples.
3. SoC-level. The IP vendor should verify representative customer configurations using a number of sample SoC designs to verify performance and quality. SoC-level verification inputs are usually provided to IP vendors by their customers. Design performance drift verification is also important.
4. Design flow tool verification. Involves the testing of any tools used to configure and generate the IP, whether the tool suite is controlled by a graphical user interface (GUI), the command-line or both.
5. Interoperability. Ask the IP vendor to demonstrate testing results for transaction and communication protocols such as AMBA and customer proprietary protocols. Also, EDA tool and verification IP integrations with key partners should be required.
6. Customer module and SoC verification. Occurs during the design, tapeout, bring-up and debug phases. The customer should be able to implement, integrate and verify the customer-configured IP at the same or higher confidence as if it were hand-coded by an internal team.
7. Customer, system-level user and quality experience. Includes system house and end-customer system lifecycle testing.

If you are asking your IP vendors for the seven levels above, and they are ready and willing to employ the people, processes and execution to ensure the results provided to you, then your design team is most likely dealing with quality IP. The seven levels above will also help SoC designers verify custom configurations.

Do not go by anticipated results. Evaluating the quality of IP requires a long-term relationship with an IP vendor and certain levels of trust must be built up over that time. Unless an IP has been deployed successfully in sufficient volume, there is no way to know what types of problems can be encountered. Problems usually lead to schedule push outs or worse. Get to market sooner with quality IP, a successful relationship with the vendor and the seven levels of verification.