What Exactly Is Multi-Physics?

Multi-physics is the new buzzword in semiconductor design and analysis, but the fuzziness of the term is a reflection of just how many new and existing problems need to be addressed simultaneously in the design flow with advanced nodes and packaging.

This disaggregation of planar SoCs and the inclusion of more processing elements, memories, interconnects, and passives inside a package has created a blanket term to describe changes in tools and methodologies. There are structural issues, physical effects, and thermal effects to contend with due to increased density, higher processing demands, and more complex workloads. And all of this is undergoing change at a rapid rate, which makes analysis much more complicated and harder to describe.

“What we simulate in IC design is obviously physics,” says Rich Goldman, director at Ansys. “You could say that’s multi-physics, but I don’t think the world thinks of that as multi-physics. For functional simulation, while there’s physics behind it, it is not a physics simulation. It may be an AND gate or an OR gate. If you simulate that, you get a one or a zero. It’s a logic abstraction of physics. In general, what we’ve known classically as IC design, including timing simulation, maybe going even to power, and certainly any digital simulation, is not considered multi-physics. SPICE is getting close, as you get into analog simulation.”

So why is the term becoming more popular now? “Multiple physical effects have been playing an important role in chip design from the very beginning,” says Roland Jancke, design methodology head in Fraunhofer IIS’ Engineering of Adaptive Systems Division. “Thermal, mechanical, and electromagnetic effects need to be considered in order to fulfill application requirements. However, recent technological developments are forcing designers to consider mechanisms from different physical domains. This needs to happen early in the development process due to their direct interaction with each other, and with the functional behavior of the chip.”

The resulting impact on tools and flows could be considerable. “Multi-physics is not the best term for it,” says Matt Grange, senior product engineer at Siemens EDA. “It’s a multi-space solution problem. It’s a convergence of different simulation environments and tools and problems, and it’s all coming to a head now that we’re moving into highly integrated dense packages.”

Two worlds converging
In the past, chips and systems were in unconnected domains, and there was a very large wall between them. Each domain used different tools, methodologies and even terminology.

“Everything inside of an IC has not been considered multi-physics, and everything outside of it has,” says Ansys’ Goldman. “They grew up separately, and ‘never the twain shall meet.’ With tools like IC compiler, they are bringing in more physics, and the line starts to get a little bit fuzzy. It gets really fuzzy when you do 3D-IC and start stacking things. Now you have to consider thermal, and you have to consider electromagnetic interference. These are things that are classic multi-physics and are now being brought into IC design through 3D-IC.”

It gets more complicated because many physical effects interplay with each other. “The physics we are concerned with comes as a result of the shift to heterogeneous packaging, where suddenly we have impacts that are beyond what’s traditionally on a single die,” says John Ferguson, product management director of Calibre nmDRC applications at Siemens EDA. “That can be from heating effects and from stress effects. Not everyone realizes that those issues have an impact on electrical behavior and electrical performance. If you’re not taking these things into consideration, then you’re going to have results in the real world that are different than what you thought they were going to be.”

Most multi-physics problems primarily arise due to advanced packaging. “With the continuous integration of functionality, these effects are becoming more prevalent,” says Andy Heinig, head of Efficient Electronics at Fraunhofer IIS/EAS. “For example, we are seeing more coupling effects between interconnects, or between interconnects and transistors from different circuits. Additionally, coupled effects from thermal influences on electrical performance are increasing in highly integrated packages. This requires more analysis.”

Coupling is layout-dependent. “A thermal analysis tool has to be aware of the interaction between different parts of design, depending on how close or how far they are from each other,” says Suhail Saif, principal product manager at Ansys. “Once the thermal analysis is complete, along with its x and y coordinates, that data is fed back to the power step, and you have to do the whole iteration again. Depending on how sensitive they are about the minute details of the thermal analysis, which is relating to the power consumption, a company may decide to stop after two or three iterations. After the second iteration, the results start making a lot of sense. And after the third iteration, the results are pretty good. You can plot how divergent each of the samples is from the final convergent result, and the variation would be all the way from 2% to 3% on the minimum side, to maybe 20% to 30% on the maximum side.”

It also couples the manufacturing process with design. “Most of the heating that happens to a chip is going to happen when you are manufacturing it,” says Siemens’ Ferguson. “That is where most of the deformation is going to come from. You may not have to think about how the chip is going to be used, depending on how long you’re going to use it and its operating conditions. With good thermal analysis, you should be able to come up with something that is reliable. The question becomes, ‘What happened beforehand? How did these chiplets get influenced by the materials that are expanding and squeezing on the chiplets. Packages are created in layers. You may have an interposer. You place a layer of chips on those, and you heat it to very high temperatures for a fairly good period of time. Other materials will expand faster than silicon. Now you cool it, and you start adding on top of that, and that’s where things start to get really interesting. For the last few years, we’ve mostly been focused on dies next to each other on the horizontal plane, but now we’re going into three dimensions. That adds more complexity. It can shrink the chiplets a little bit, so you have to take that into consideration.”

And that wraps back to electrical behavior. “Ultra-scaled semiconductor technologies are using mechanical pre-stress in the gate area in order to increase carrier mobility,” says Fraunhofer’s Jancke. “If further mechanical stress is introduced during back-end processing, packaging, or even in-field operation, the intended pre-stress may either be increased or decreased, which directly affects performance of the circuit and could hamper design targets.”

Mechanical needs to be considered along with electrical. “Mechanical is critical because you’re stressing the chips and you’re cracking your solder balls, and they may stop working,” says Goldman. “You need to do mechanical simulation on the 3D-IC.”

Everything is becoming interlinked. “As a direct consequence of technology scaling and advanced integration methods, like 2.5D and 3D integration, distances are shrinking in chip packages,” says Jancke. “Power, on the other hand, does not shrink at the same scale. Thermal effects become more dominant. On top of that, strong thermal gradients — with different thermal expansion coefficients in the multi-fold materials involved — are generating thermo-mechanical interactions. So electro-thermo-mechanical effects are the consequence, which is truly multi-physics.”

Impact on tools and methodology
While multi-physics is a back-end issue, it has to be considered early in the flow. “The problem is that simulations run separately, and there is no direct process when issues arise,” says Fraunhofer’s Heinig. “Typically, the design is revisited, and an alternative approach is tried, but this is not very systematic. The current idea is to represent the effects more clearly in the system models, making them accessible at this level. This would allow for much simpler and more systematic comparisons of many variations.”

Thermal, like power, is becoming a systemic concern. “Tools and flows are shifting further to the left because you can’t wait until the end, where your package is done, to run these tools,” says Siemens’ Grange. “You need to start before you have your layouts completed. You need to figure out placement, when you’re looking at feasibility of the placement. Can this die go on top of that one, in that place, and what stress is going to be there? If you have early power estimates, you can look at thermal. And you need to run these all the way through the design flow, not just at the end.”

Many of the physics have implications early in the flow. “Shift-left requires design teams to consider issues of electromagnetic interference (EMI)/electromagnetic compatibility (EMC), as well as power integrity (PI), signal integrity (SI), and thermal integrity earlier in the design process,” says Sherry Hess, senior product management group director for multi-physics system analysis at Cadence. “A comprehensive systems design and analysis offering that ensures the system works under wide-ranging operating conditions must not only include the IC, IC package, and PCB design platforms, but must also integrate their inherent multi-physics phenomena, as well.”

The question is how to take care of multiple, mutually influencing effects when many of them are done in discrete silos today? “Circuits designers are used to working with simulation tools for voltages and currents,” says Jancke. “But where is the pin in a transistor model to apply mechanical stress? Such effects are handled by completely different simulators, like FEM tools.

In the future, more interfaces are needed between the different views on a chip design. The circuit-level simulation needs to have information about the location and orientation of the devices in order to take thermal and mechanical interactions into account. Also, packaging information needs to be provided in order to correctly place devices, being aware of thermal, mechanical, or electromagnetic interference from nearby chips.”

Changing fundamental device models is difficult. “The impacts of stress are in the device model,” says Ferguson. “For thermal, it’s a little bit easier, because you can add thermal properties into a netlist. It could be part of a wire. It could be anywhere. You just tag the thermal property. But for stress, we don’t have the same concept in the industry yet. The idea that we push is to say, ‘I’ve got this traditional device model. Sometimes those device models have a way to pass information about the change in mobility. You can use that and update it.’ In most simulation tools, that’s not so easily done. Then, it means you need to make an adjustment on the model.”

It is also causing more cooperation between EDA companies. “If you look at 3D-IC compiler from Synopsys, they realized they needed some of this multi physics, and they incorporated the Red Hawk technology from Ansys into the compiler,” says Goldman. “We integrated the solver, not the tool, into the Synopsys product. That’s a good example of merging what was classically outside and bringing it inside. We’re doing the same thing with thermal. Another tool for electromagnetic antennas and radar, is now needed inside of the package for 3D-IC to handle electromagnetic interference.”

A problem with timescales
Heat, thermal, and stress happen over time. “When you power up the chip, it starts heating and that makes the materials change their behavior,” says Ferguson. “Both the heating and the materials change will impact the electrical behavior. But that implies that what you understood from your initial power analysis was correct. In reality, it’s not. It takes some time for you to come to a steady state, and that’s a new phenomenon. We didn’t have to worry about this with a single die, except perhaps a little bit with RF, or some elements that were more sensitive, or if you were doing exotic materials in your chips. But in traditional silicon-based chips, you didn’t have to worry too much because you had ways to dissipate heat. You knew where everything was going to be, what it could withstand, and what it couldn’t. Now it’s much more complex, where you have different materials.”

Another problem is that the timescales are different, meaning that tools have to take a different approach when brought together.

Consider power and thermal, for example. “Power uses a small timescale, and thermal needs a long timescale,” says Ansys’ Saif. “Theoretically, if you try to solve that, it is going to take a lot of compute and time, which is not practical. Instead, we start with power, which requires a small timescale, and we try to aggregate the results over a longer period of time. We chunk over a long duration of time. For example, 15 seconds or 20 seconds might be the goal for a thermal analysis.  If we take that 20 seconds and divide it into 100 millisecond pieces, we do power simulation for those small 100 millisecond periods and generate aggregate power number for each of them. Once we have that quick 100 millisecond analysis done, we combine those samples together. Imagine if you are putting them in sequence, it becomes a waveform. It is not a very accurate waveform, but after 2,000 or 30,000 pieces, it resembles a waveform. That is what we feed into thermal analysis. This is one way of making it practical for power tools, as well as thermal tools, to understand the same timeframe when doing power and thermal analysis.”

Now the thermal analysis is done, the results have to be fed back. “The feedback loop also follows the same split,” says Saif. “The thermal tool does its analysis for the entire duration, and then we again break it into those small pieces and feed it back to each of the 100 millisecond windows at the power stage. When you do this splitting of the entire analysis result, you lose some accuracy, but that is the tradeoff. What you gain is the same context given to both the tools, so they are both looking at the same design over the same time period and doing the same analysis.”

Conclusion
Everything in semiconductor design is driven by physics, but in the past the industry was able to abstract the details and provide enough encapsulation that gates and wires could be essentially considered to be independent elements. With scaling and advanced packaging, those abstractions and encapsulations are breaking down. The impacts, although fairly small, remain significant when dealing with devices where margins are tight to begin with.

The chip industry does not have all the answers today. The first set of tools and flows are beginning to appear, but it will take time before all of the interactions are fully understood and solutions developed — and possibly some new additions to the industry’s lexicon.

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