A Closer Look At One-Time Programmable Embedded Memory

Only one kind of embedded NVM is process-scalable and high density.


Being the first month of the year, chip designers have probably reflected on 2015 and are thinking ahead to upcoming projects this year. They want to produce a product that reflects tomorrow’s needs for electronic devices that include low power, high performance and high security. Now, they’re thinking about embedded memory, a requirement for all electronic devices. It’s captured the attention of chip designers in large measure because it’s taking up more than 50% of the die area, all the while being the most critical component for timing and power.

Chip designers make their embedded memory technology selections based on specific application requirements that force tradeoffs between volatile and non-volatile, and high performance versus low power. Non-volatile memory is often chosen because it fills specific system requirements that maintain the state of the memory after power-off. These tradeoffs, however, become more difficult when there is a standard logic CMOS chip requirement for embedded NVM because CMOS Logic NVM technologies are limited to fuse, antifuse and floating gate.

Of the three, the only eNVM technology type that is process-scalable and high density is one-time programmable (OTP) or antifuse. It’s one of the more popular because it is low power and high performance, and tightly integrates high-density permanent memory with digital logic in CMOS technology.

OTP eNVM is viewed as the optimal embedded memory for security applications, SoC configurability and manufacturability and usability. Let’s take a closer look.

Security has become a huge concern for chip designers as they recognize that the encryption key and/or ID used in a security scheme is where a hack or attack will happen. The CMOS logic antifuse provides physical layer security for information stored in hardware.

For system designers, SoC configurability can take on many different forms. Adding configurability reduces the number of unique mask sets needed to support a more complex product line or range of similar products. Ultimately, a common platform architecture might be used to reduce R&D costs in a common product segment where features can be segmented or further differentiated in post-production. The primary benefits are reduced engineering, time-to-market and inventory risk without significantly increasing the unit cost.

Common forms of SoC configurability can be achieved through the storage of boot code in a CMOS antifuse OTP memory module. This in-system programmable boot code can be used to pass configuration information to code stored in a less expensive masked ROM. Similarly, system configuration and/or firmware parameters can be stored in OTP to better leverage embedded OTP memory.

Storing system state information at any stage of manufacturing or the product lifecycle gives chip makers new ways to use hardware. The ability to adapt to any system change over a product’s lifecycle requires eNVM. By tightly integrating OTP in the SoC, designers can produce highly differentiated product advantages at any stage.

New architectural SoC features require tightly integrated permanent memory on chip. CMOS logic antifuse like OTP enables designers and architects to imagine new uses and additional applications that bring substantial value to most segments of the Semiconductor industry. The ability to permanently maintain state information within the SoC device itself will simplify SoC interfaces and usability accruing significant product advantages over competing technologies. That’s why one-time programmable non-volatile memory has become the most sought-after embedded memory.

Also, a new breakthrough technology reduces power by 10X in embedded memory! Read this whitepaper to learn more.


Bo Lu says:

What is the max size of OTP on TSMC40nm LP you can get? Normally efuse size is in the range of 2-5Kb, but is 400kb size possible?

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