A Performance-Aware Framework For Co-Optimizing Floorplan And Performance Of Chiplet-Based Architecture


A technical paper titled “Floorplet: Performance-aware Floorplan Framework for Chiplet Integration” was published by researchers at Chinese University of Hong Kong and University of California Berkeley.


“A chiplet is an integrated circuit that encompasses a well-defined subset of an overall system’s functionality. In contrast to traditional monolithic system-on-chips (SoCs), chiplet-based architecture can reduce costs and increase reusability, representing a promising avenue for continuing Moore’s Law. Despite the advantages of multi-chiplet architectures, floorplan design in a chiplet-based architecture has received limited attention. Conflicts between cost and performance necessitate a trade-off in chiplet floorplan design since additional latency introduced by advanced packaging can decrease performance. Consequently, balancing power, performance, cost, area, and reliability is of paramount importance. To address this challenge, we propose Floorplet, a framework comprising simulation tools for performance reporting and comprehensive models for cost and reliability optimization. Our framework employs the open-source Gem5 simulator to establish the relationship between performance and floorplan for the first time, guiding the floorplan optimization of multi-chiplet architecture. The experimental results show that our framework decreases inter-chiplet communication costs by 24.81%.”

Find the technical paper here. Published August 2023 (preprint).

Chen, Shixin, Shanyi Li, Zhen Zhuang, Su Zheng, Zheng Liang, Tsung-Yi Ho, Bei Yu, and Alberto L. Sangiovanni-Vincentelli. “Floorplet: Performance-aware Floorplan Framework for Chiplet Integration.” arXiv preprint arXiv:2308.01672 (2023).

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