A Simple Way To Improve Automotive In-System Test

The remarkable growth in automotive IC design has prompted a focus on ISO26262 functional safety compliance, which includes both high-quality manufacturing test and a minimum stuck-at test coverage of 90% for in-system test. Designers must also control IC test data volumes, test application times, and test costs. A new test point technology that improves in-system test coverage and reduces pattern count is poised to become a new standard in DFT (design for test) methodologies for mission-critical ICs.

Perhaps the most popular of the newer DFT strategies for automotive ICs is hybrid ATPG/logic built-in self-test (LBIST). The once-separate ATPG and LBIST technologies have merged to the point where compression IP is being re-used to apply BIST tests. The result is smaller test sets, higher fault coverage, and the integration of self-test required by ISO 26262. The latest leap in test efficiency is a new kind of test point that works with hybrid ATPG/LBIST with more efficiency than test points for either ATPG or LBIST separately.

What is Hybrid ATPG/LBIST?

Embedded ATPG compression has been the standard method of manufacturing test for many years. LBIST was introduced for board, system, and in-field tests—a key requirement in mission-critical automotive ICs. LBIST applies semi-random patterns to the circuit in place of a deterministic stimulus, collecting the circuit response in a Multi-Input Signature Register (MISR) which requires the circuit to be “X-free,” meaning that no unknown values are observed. You achieve X-free design by controlling the propagation of random or unknown data from sources within a circuit. LBIST excels as the in-system test method of choice because the generation of patterns and collecting of signatures is fully located on-chip. However, it may take a large number of patterns, and a relatively long amount of time, to achieve required coverage goals. The MISR-based signature may be compared on-chip (such as in an automotive implementation), or it may be scanned off-chip and compared externally.

In addition to stuck-at and transition delay tests, ATPG offers high defect detection targeting specialized fault models including timing-aware, cell-aware, path delay, and bridging faults. ATPG can deliver the high-quality manufacturing test required for mission-critical ICs, but it also presents challenges in the form of large test pattern sets that drive up test costs and time, making ATPG a non-ideal solution for in-system testing.

The combination of these two testing methods in a hybridized version allows for testing of automotive IC designs in various scenarios: wafer, packaged, and in-system. Using both methods, however, could take up chip area because the LBIST LFSR (linear feedback shift register) and the compression decompressor for ATPG used different logic, even though their functional purposes are similar. There are now solutions that combine the logic from embedded compression ATPG and LBIST to enable this hybrid ATPG/LBIST approach without the area penalty. This hybrid ATPG/LBIST strategy has become widely used by designers of automotive ICs. Figure 1 illustrates the combined logic architecture of hybrid TK/LBIST.

Figure 1. The logic architecture of Mentor’s Tessent TestKompress TK/LBIST, a hybrid ATPG/LBIST solution, with test points.

What are Hybrid ATPG/LBIST test points?

Test points are dedicated design structures used to improve the test results. Traditional LBIST test points improve results by breaking up areas within the circuit that are random-pattern resistant, such as large blocks of logic focused on encoding or decoding. There are also relatively new test points specifically for on-chip compression/ATPG, which automatically insert gates so that parallel logic cones share the same ATPG patterns. ATPG test points typically reduce ATPG pattern count by 2-4X beyond what is achieved with on-chip compression alone.

Neither ATPG nor BIST test points are individually suited for use in a hybrid ATPG/BIST environment. This means that the increasing number of designers implementing a hybrid ATPG/LBIST approach must run test point insertion twice to achieve the best result for both ATPG and BIST tests.

The new hybrid test point technology combines and improves upon previous test point algorithms to improve ATPG compression as well as random pattern coverage further. These new test points are inserted in a single pass, which streamlines the design flow.

How do Hybrid ATPG/LBIST test points work?

The new hybrid test point technology combines the co-targeting of multiple test point goals (pattern count reduction and BIST coverage) with more advanced test point analysis and insertion algorithms. The benefits for automotive IC designs is better in-system test coverage to comply with the ISO 26262 standard. If LBIST stuck-at coverage is already 90%, hybrid test points can maintain that with up to 10x fewer LBIST patterns.

Fault simulation was run up to 16k LBIST vectors to compare baseline LBIST test-coverage with that of LBIST test points and hybrid test points. Compared to baseline (no test points), the average coverage improvement with LBIST test points was 5.6%. The coverage improvement with hybrid test points was 9.5%. Table 1 shows the results.

Table 1: Stuck-at fault test coverage achieved after 16k patterns.

Several large semiconductor companies have evaluated hybrid test points as a replacement for separate LBIST and ATPG test point insertion in hybrid ATPG/LBIST testing strategies. All found that the run-time of the newer insertion algorithms is much faster than previous algorithms, providing savings of 20X on average. Improved LBIST coverage for automotive customers targeting in-system test means 90% test coverage targets are achieved faster.

More Information: Improving In-System Test with Tessent VersaPoint Test Point Technology