A View Across The Siliconscape

Assessing product performance, utilization, and longevity with in-chip monitoring.


What would it look like if you had the magical ability to look inside a chip and cast your eyes across the tumultuous activities within the silicon itself? If you could gaze into the die and see the real-time peaks and troughs of voltage supply, stressed areas with high activity and heat and areas of calm where uneven workloads create idle processor cores. A vision of the chip landscape, seascape, or even a siliconscape that is constantly changing during operation. Stay with me for just a moment further. What would it look like to then take this magical view of siliconscapes between millions of devices being manufactured at the foundry, tested prior to deployment, or released to the field as a fleet of products?

My last blog, Completing The Silicon Lifecycle Management Puzzle, was a reflection on the opportunity that is now presented to the semiconductor industry. The blog highlighted the huge value of embedding monitors and sensors within today’s silicon designs and how those structures enable rich sources of data to be analyzed to the benefit of product and system optimization, as well as reliability. An opportunity whereby each step of the silicon chip’s lifecycle within data center, automotive, or consumer applications can be assessed from the process of design through to end-of-life prediction.

The evolution of the automobile during the early 20th century saw users (otherwise known as drivers) benefit and gain increased convenience from the progress of early real-time measurement concepts such as fuel gauges, engine pressure monitors, and oil temperature sensors. A strong reliance on such technology meant that to dispense with it would become unthinkable to drivers. On the contrary, the game was on to develop more accurate, faster reacting and more reliable dashboards. If, like me, you’ve owned an old car with a failing fuel gauge or speedometer you’ll know how anxious the driving experience can become!

In a similar way, in-chip monitors are now critical to the successful operation and performance of finFET devices. Embedded sensors are growing in importance and have become a critical link in the chain. Life observations generally lead us to conclude that importance is proportionally related to the pain or inconvenience in the event of failure.

From the perspective of assessing the functional behavior of a chip, what happens should the monitors that feed variable clocking, adaptive voltage, or device protection schemes that you rely upon fail and what could the consequences be? Perhaps a cooling fan doesn’t switch on, a low supply alert is not given, a corrupted thermal measurement dramatically increases clock or supply levels, all leading to a catastrophic failure of not only the chip but the product itself. It becomes obvious at this point that low latency, responsive, catastrophic trip protection circuits are required, especially when considering that localized die temperature can rise rapidly, within milliseconds. Combined with self-checking monitors that ensure their own health status, we start to mitigate potential failure situations. At the very least, with such protections and approaches, we can seek to react safely should failure occur, which is a particularly hot topic for automotive applications.

From a performance assessment perspective, an opportunity continues to grow with respect to the measurement of margin in designs. Within complex SoCs, optimization can be delivered by suppressing voltage, as saving a few millivolts pays good dividends in power savings since energy use is proportional to voltage squared. There is a demand to improve techniques to suppress supplies and measure the margin of operation available, which in turn produces impactful results when considering data center energy consumption or battery life for consumer products. The gains for measuring the marginality of critical paths within complex digital chip designs are significant.

So, the two key challenges of performance and reliability dictate the direction of silicon lifecycle measurement and analysis. The siliconscape is still largely a greenfield space for us to explore and travel through, where close behind better understanding lies the opportunity for greater product performance, utilization, and longevity. Silicon lifecycle management continues to provide the vehicle for us to embark on this new and exciting journey.

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